Atomic operations on i386/amd64

[Scott Long]

John Baldwin wrote:
> On Thursday 05 August 2004 01:04 am, Tim Robbins wrote:
> 
>>Is there any particular reason why atomic_load_acq_*() and
>>atomic_store_rel_*() are implemented with CMPXCHG and XCHG instead of
>>MOV on i386/amd64 UP?
> 
> 
> Actually, using mov instead of lock xchg for store_rel reduced performance in 
> some benchmarks Scott ran on an SMP machine, I'm guessing due to the higher 
> latency of locks becoming available to other CPUs.  I'm still waiting for 
> benchmark results on UP to see if the change should be made under #ifndef SMP 
> or some such.
> 

Your patch appears to slightly pessimize UP as well and SMP.

Scott