Atomic operations on i386/amd64

John Baldwin jhb at
Fri Aug 6 10:46:48 PDT 2004

On Thursday 05 August 2004 11:43 pm, Scott Long wrote:
> John Baldwin wrote:
> > On Thursday 05 August 2004 01:04 am, Tim Robbins wrote:
> >>Is there any particular reason why atomic_load_acq_*() and
> >>atomic_store_rel_*() are implemented with CMPXCHG and XCHG instead of
> >>MOV on i386/amd64 UP?
> >
> > Actually, using mov instead of lock xchg for store_rel reduced
> > performance in some benchmarks Scott ran on an SMP machine, I'm guessing
> > due to the higher latency of locks becoming available to other CPUs.  I'm
> > still waiting for benchmark results on UP to see if the change should be
> > made under #ifndef SMP or some such.
> Your patch appears to slightly pessimize UP as well and SMP.

Hmm, well so much for LOCK XCHG being evil then I guess.  This points out that 
we should really benchmark the *FENCE changes to see if they help or hurt as 
well before committing them.

John Baldwin <jhb at>  <><
"Power Users Use the Power to Serve"  =

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