svn commit: r198341 - in head/sys: amd64/amd64 arm/arm arm/mv i386/i386 i386/xen ia64/ia64 kern mips/mips powerpc/aim powerpc/booke powerpc/include powerpc/powerpc sparc64/sparc64 sun4v/sun4v vm

[Marcel Moolenaar]

On Oct 22, 2009, at 2:10 AM, Rafal Jaworowski wrote:

>
> On 2009-10-21, at 20:38, Marcel Moolenaar wrote:
>
>> The key property of this change is that the I-cache is made coherent
>> *after* writes have been done. Doing it in the PMAP layer when adding
>> or changing a mapping means that the I-cache is made coherent  
>> *before*
>> any writes happen. The difference is key when the I-cache prefetches.
>
> Marcel, does this new approach help with your problems on MV-78xxx  
> with SATA when executing binaries was failing with various signals  
> etc. (and the suspicions were this was due to some i-cache  
> incoherency)?

This commit only adds I-cache synchronisation to ptrace(2) so
that breakpoints work reliably. Note that the PMAP layer for
ARM needs to have a proper implementation, because breakpoints
don't work reliably. Unfortunately, the PMAP code is not well
suited for non-current PMAP operations. I'm looking into it...

In any case: I'll be working on moving I-cache coherency from
PMAP to MI where sensible to make sure we synchronize after the
memory update and not before (or multiple times in an attempt
to plaster over the cracks). I expect that in the end it'll
have helped... :-)

-- 
Marcel Moolenaar
xcllnt at mac.com