svn commit: r341117 - head/sys/dev/sfxge/common
Andrew Rybchenko
arybchik at FreeBSD.org
Wed Nov 28 06:56:02 UTC 2018
Author: arybchik
Date: Wed Nov 28 06:55:59 2018
New Revision: 341117
URL: https://svnweb.freebsd.org/changeset/base/341117
Log:
sfxge(4): move vector config to ef10 NIC board config
Submitted by: Andy Moreton <amoreton at solarflare.com>
Sponsored by: Solarflare Communications, Inc.
Differential Revision: https://reviews.freebsd.org/D18193
Modified:
head/sys/dev/sfxge/common/ef10_nic.c
head/sys/dev/sfxge/common/hunt_nic.c
head/sys/dev/sfxge/common/medford2_nic.c (contents, props changed)
head/sys/dev/sfxge/common/medford_nic.c
Modified: head/sys/dev/sfxge/common/ef10_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:55:47 2018 (r341116)
+++ head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:55:59 2018 (r341117)
@@ -1578,6 +1578,7 @@ ef10_nic_board_cfg(
ef10_link_state_t els;
efx_port_t *epp = &(enp->en_port);
uint32_t board_type = 0;
+ uint32_t base, nvec;
uint32_t port;
uint32_t pf;
uint32_t vf;
@@ -1694,13 +1695,27 @@ ef10_nic_board_cfg(
encp->enc_buftbl_limit = 0xFFFFFFFF;
+ /* Get interrupt vector limits */
+ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
+ if (EFX_PCI_FUNCTION_IS_PF(encp))
+ goto fail9;
+
+ /* Ignore error (cannot query vector limits from a VF). */
+ base = 0;
+ nvec = 1024;
+ }
+ encp->enc_intr_vec_base = base;
+ encp->enc_intr_limit = nvec;
+
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
- goto fail9;
+ goto fail10;
return (0);
+fail10:
+ EFSYS_PROBE(fail10);
fail9:
EFSYS_PROBE(fail9);
fail8:
Modified: head/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:55:47 2018 (r341116)
+++ head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:55:59 2018 (r341117)
@@ -108,7 +108,6 @@ hunt_board_cfg(
uint32_t mask;
uint32_t flags;
uint32_t sysclk, dpcpu_clk;
- uint32_t base, nvec;
uint32_t bandwidth;
efx_rc_t rc;
@@ -253,20 +252,8 @@ hunt_board_cfg(
goto fail5;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail6;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
- goto fail7;
+ goto fail6;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -274,8 +261,6 @@ hunt_board_cfg(
return (0);
-fail7:
- EFSYS_PROBE(fail7);
fail6:
EFSYS_PROBE(fail6);
fail5:
Modified: head/sys/dev/sfxge/common/medford2_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:55:47 2018 (r341116)
+++ head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:55:59 2018 (r341117)
@@ -80,7 +80,6 @@ medford2_board_cfg(
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
- uint32_t base, nvec;
uint32_t end_padding;
uint32_t bandwidth;
uint32_t vi_window_shift;
@@ -188,18 +187,6 @@ medford2_board_cfg(
goto fail5;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail6;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.
@@ -208,14 +195,12 @@ medford2_board_cfg(
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail7;
+ goto fail6;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail7:
- EFSYS_PROBE(fail7);
fail6:
EFSYS_PROBE(fail6);
fail5:
Modified: head/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:55:47 2018 (r341116)
+++ head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:55:59 2018 (r341117)
@@ -76,7 +76,6 @@ medford_board_cfg(
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
- uint32_t base, nvec;
uint32_t end_padding;
uint32_t bandwidth;
efx_rc_t rc;
@@ -185,18 +184,6 @@ medford_board_cfg(
goto fail4;
encp->enc_privilege_mask = mask;
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail5;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
/*
* Medford stores a single global copy of VPD, not per-PF as on
* Huntington.
@@ -205,14 +192,12 @@ medford_board_cfg(
rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail6;
+ goto fail5;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail6:
- EFSYS_PROBE(fail6);
fail5:
EFSYS_PROBE(fail5);
fail4:
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