svn commit: r341116 - head/sys/dev/sfxge/common

[Andrew Rybchenko]

Author: arybchik
Date: Wed Nov 28 06:55:47 2018
New Revision: 341116
URL: https://svnweb.freebsd.org/changeset/base/341116

Log:
  sfxge(4): move limits config to ef10 NIC board config
  
  Submitted by:   Andy Moreton <amoreton at solarflare.com>
  Sponsored by:   Solarflare Communications, Inc.
  Differential Revision:  https://reviews.freebsd.org/D18192

Modified:
  head/sys/dev/sfxge/common/ef10_nic.c
  head/sys/dev/sfxge/common/hunt_nic.c
  head/sys/dev/sfxge/common/medford2_nic.c   (contents, props changed)
  head/sys/dev/sfxge/common/medford_nic.c

Modified: head/sys/dev/sfxge/common/ef10_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c	Wed Nov 28 06:55:36 2018	(r341115)
+++ head/sys/dev/sfxge/common/ef10_nic.c	Wed Nov 28 06:55:47 2018	(r341116)
@@ -1682,6 +1682,17 @@ ef10_nic_board_cfg(
 	 */
 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
+	/*
+	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
+	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
+	 * resources (allocated to this PCIe function), which is zero until
+	 * after we have allocated VIs.
+	 */
+	encp->enc_evq_limit = 1024;
+	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
+	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
+
+	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	/* Get remaining controller-specific board config */
 	if ((rc = enop->eno_board_cfg(enp)) != 0)

Modified: head/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/hunt_nic.c	Wed Nov 28 06:55:36 2018	(r341115)
+++ head/sys/dev/sfxge/common/hunt_nic.c	Wed Nov 28 06:55:47 2018	(r341116)
@@ -233,22 +233,10 @@ hunt_board_cfg(
 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 
 	/*
-	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
-	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
-	 * resources (allocated to this PCIe function), which is zero until
-	 * after we have allocated VIs.
-	 */
-	encp->enc_evq_limit = 1024;
-	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
-	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
-	/*
 	 * The workaround for bug35388 uses the top bit of transmit queue
 	 * descriptor writes, preventing the use of 4096 descriptor TXQs.
 	 */
 	encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
-
-	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 	encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;

Modified: head/sys/dev/sfxge/common/medford2_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford2_nic.c	Wed Nov 28 06:55:36 2018	(r341115)
+++ head/sys/dev/sfxge/common/medford2_nic.c	Wed Nov 28 06:55:47 2018	(r341116)
@@ -167,23 +167,11 @@ medford2_board_cfg(
 	encp->enc_rx_buf_align_end = end_padding;
 
 	/*
-	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
-	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
-	 * resources (allocated to this PCIe function), which is zero until
-	 * after we have allocated VIs.
-	 */
-	encp->enc_evq_limit = 1024;
-	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
-	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
-	/*
 	 * The maximum supported transmit queue size is 2048. TXQs with 4096
 	 * descriptors are not supported as the top bit is used for vfifo
 	 * stuffing.
 	 */
 	encp->enc_txq_max_ndescs = 2048;
-
-	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 	encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;

Modified: head/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford_nic.c	Wed Nov 28 06:55:36 2018	(r341115)
+++ head/sys/dev/sfxge/common/medford_nic.c	Wed Nov 28 06:55:47 2018	(r341116)
@@ -164,23 +164,11 @@ medford_board_cfg(
 	encp->enc_rx_buf_align_end = end_padding;
 
 	/*
-	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
-	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
-	 * resources (allocated to this PCIe function), which is zero until
-	 * after we have allocated VIs.
-	 */
-	encp->enc_evq_limit = 1024;
-	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
-	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
-	/*
 	 * The maximum supported transmit queue size is 2048. TXQs with 4096
 	 * descriptors are not supported as the top bit is used for vfifo
 	 * stuffing.
 	 */
 	encp->enc_txq_max_ndescs = 2048;
-
-	encp->enc_buftbl_limit = 0xFFFFFFFF;
 
 	EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;