FreeBSD TDMA: Legalizing 440MHz 802.11 modems
Adrian Chadd
adrian at freebsd.org
Wed Aug 27 23:47:04 UTC 2014
On 27 August 2014 16:38, Bart Kus <me at bartk.us> wrote:
> I'm guessing the chip generates its own internal clocks from an external
> reference. Can that PLL be slowed down ahead of timers overflowing?
> Hopefully the PCI clock is generated independently.
Yeah, that's what you're slowing down - you program the PLL.
The PCI clock is generated separately.
> Also, I think Mikrotik implements narrower bands by dropping subcarriers
> instead of slowing down their symbol rates. I'll try to get a good spectrum
> picture of their 5MHz mode tonight. Keeping the subcarrier symbol rates
> relatively higher might offset some analog droops, at the cost of OFDM skirt
> sharpness.
Hey cool, if they're doing that then I should likely go digging for
the PHY documentation for the AR5414 and find out.
> Also, a slight correction. I think you meant the subs are 312.5kHz wide,
> which would result in a 200kHz emission having 3.125kHz wide subs. Or,
> perhaps more realistically, running at 1/128th the speed, 2.44140625kHz
> wide. How can you not love a number like that? :)
Someone else can do better math, I'm busy doing non-wifi at the moment. :)
But, it really is 20MHz / 64 carriers == each subcarrier width.
> Does the project have a map of all these clocks + timers which might need
> tweaking for spectrum reduction? I know you can't cite original Atheros
> docs, but perhaps there's been derivative documentation works created?
Not at the moment I'm afraid. I haven't really dug into that level of
detail. I documented what's needed for 5 and 10MHz modes.
However - there's an analog filter that I don't know if it's
programmable or not. It's used for both transmit and receive
filtering. I know on these chips it can do 5/10/20/40 but I don't know
if it's an arbitrary width.
-a
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