FreeBSD TDMA: Legalizing 440MHz 802.11 modems

[Bart Kus]

I'm guessing the chip generates its own internal clocks from an external 
reference.  Can that PLL be slowed down ahead of timers overflowing?  
Hopefully the PCI clock is generated independently.

Also, I think Mikrotik implements narrower bands by dropping subcarriers 
instead of slowing down their symbol rates.  I'll try to get a good 
spectrum picture of their 5MHz mode tonight. Keeping the subcarrier 
symbol rates relatively higher might offset some analog droops, at the 
cost of OFDM skirt sharpness.

Also, a slight correction.  I think you meant the subs are 312.5kHz 
wide, which would result in a 200kHz emission having 3.125kHz wide 
subs.  Or, perhaps more realistically, running at 1/128th the speed, 
2.44140625kHz wide.  How can you not love a number like that? :)

Does the project have a map of all these clocks + timers which might 
need tweaking for spectrum reduction?  I know you can't cite original 
Atheros docs, but perhaps there's been derivative documentation works 
created?

--Bart


On 08/27/2014 04:13 PM, Adrian Chadd wrote:
> On 27 August 2014 16:09, Bart Kus <me at bartk.us> wrote:
>> Is the underclocking affecting the digital domain only?  Or would there be
>> some analog frequency response curves that would start falling off too?  If
>> it's a digital-only underclock I don't see why there would be any
>> degradation (aside from the obvious speed decrease).  Is this easily
>> testable somehow, with a single clock variable?
> It isn't a single clock variable. The chip is a huge state machine and
> lots of timers, so all of the timing related things that are counts
> that reflect time (eg number of ticks for 802.11 things to occur) need
> to be recalculated.
>
>> Yes, the subcarriers would get really narrow, but the sampling time would
>> increase proportionately, so the FFT resolution would stay the same.  I
>> wonder if we'd be exceeding the hold time of the S&H circuit(s)...  I don't
>> really know anything about these chips, just making wild ass guesses based
>> on generic modem architecture.  :)
> Well, there's an FFT going on, and you still will have 52 subcarriers,
> so divide your 200KHz up into 64 bins (52 subcarriers + guard bits +
> sync tones.)
>
> normally for 20MHz they're 31.25KHz wide.
>
> For 200KHz that's 0.3125KHz wide, or 312.5Hz wide. There's not a lot
> of gap between each carrier and we aren't over-sampling. I don't think
> the chip was ever really designed for that.
>
> Also yes, there's AGC and other bits that have likely only been
> characterised for a max hold time of hm, 12mS? Whatever the 1MHz CCK *
> maximum packet length is.
>
>
> -a