huge nanosleep variance on 11-stable
Ian Smith
smithi at nimnet.asn.au
Thu Nov 3 04:09:46 UTC 2016
On Wed, 2 Nov 2016 18:28:08 +0200, Konstantin Belousov wrote:
> On Wed, Nov 02, 2016 at 09:18:15AM -0700, Jason Harmening wrote:
> > I think you are probably right. Hacking out the Intel-specific
> > additions to C-state parsing in acpi_cpu_cx_cst() from r282678 (thus
> > going back to sti;hlt instead of monitor+mwait at C1) fixed the problem
> > for me. But r282678 also had the effect of enabling C2 and C3 on my
> > system, because ACPI only presents MWAIT entries for those states and
> > not p_lvlx.
> You can do the same with "debug.acpi.disabled=mwait" loader tunable
> without hacking the code. And set sysctl hw.acpi.cpu.cx_lowest to C1 to
> enforce use of hlt instruction even when mwait states were requested.
But hw.acpi.cpu.cx_lowest=C1 disables C2 & C3 etc, and Jason wanted
those - but without using mwait - if I've read him right?
cheers, Ian
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