Sun Netra X1 -- LOM: errors after clearing ram, etc.
kimble
kimble at spmpx220.com
Fri Jan 8 22:10:27 UTC 2010
try putting some PC133 ECC/Registered memory in it... the X1 doesnt like NON-ECC/non registered ram .
On Jan 8, 2010, at 2:46 PM, Craig Butler wrote:
> On 07/01/2010 14:21, Zach Wendell wrote:
>> Anyone have any ideas about the LOM output below? Just keeps spitting out
>> the same thing over and over...
>>
>> Currently there are no drives installed (waiting for a coworker to bring in
>> an extra HDD and CD-ROM drive so we can install BSD), but there is a stick
>> of non-ECC PC133, 128MB ram installed.
>>
>> I have 3 sticks of non-ECC PC133, and one stick of non-ECC PC100 ram, all
>> 128MB. 2 of them immediately throw a "no memory installed, will not proceed"
>> error -- obviously those are bad (or most likely). The other 2 do what
>> you'll see below... So far, I've only tried one stick at a time, to rule out
>> bad combos, etc.
>>
>> Thanks in advance!
>> ~zmw
>>
>>
>>
>>
>>
>> lom>
>> LOM event: +0h31m28s host power on
>> `
>> Processor Speed = [Speed Jumper = 7] 400 MHz Baud rate is 9600
>> 8 Data bits, 1 stop bits, no parity (configured from lom)
>>
>> Firmware CORE Sun Microsystems, Inc.
>> @(#) core 1.0.1 2001/02/19 09:55
>> Hardware Power ON
>> Verifying NVRAM...Done
>> Bootmode is 0
>> MCR0 = 36a0b004
>> MCR1 = c0804000
>> MCR2 = f110006
>> MCR3 = 6
>> Ecache Size = 256 KB
>> NVRAM Test
>> Icache Test
>> Dcache Test
>> MMU Test
>> Ecache Tag Addr Test
>> Ecache RAM Addr Test
>> Clearing E$ Tags Done
>> Clearing I/D TLBs Done
>> Probing memory
>> Done
>> MEMBASE=0x0
>> MEMSIZE=0x8000000
>> Data Line Test
>> Core Memory Test
>>
>> Processor Speed = 400 MHz
>> Baud rate is 9600
>> 8 Data bits, 1 stop bits, no parity (configured from lom)
>>
>> Firmware CORE Sun Microsystems, Inc.
>> @(#) core 1.0.1 2001/02/19 09:55
>> Software Power ON
>> Verifying NVRAM...Done
>> Bootmode is 0
>> MCR0 = 36a0b004
>> MCR1 = c0804000
>> MCR2 = f110006
>> MCR3 = 6
>> Ecache Size = 256 KB
>> Clearing E$ Tags Done
>> Clearing I/D TLBs Done
>> Probing memory
>> Done
>> MEMBASE=0x0
>> MEMSIZE=0x8000000
>> Clearing memory...Done
>> Turing ON MMUs Done
>> Copy ROM to RAM (148440 bytes) Done
>> Orig PC=0x1fff0007efc New PC=0xf0f07f54
>>
>> ******************************
>> ****************
>> PSTATE=0000000000000015 TBA=00000000f0f00000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=00c0 TPC=00000000f0f0b3f0 TNPC=00000000f0f0b3f4
>> TL=0004 TT=0034 TPC=00000000f0f05800 TNPC=00000000f0f05804
>> TL=0003 TT=00c0 TPC=00000000f0f0b3f0 TNPC=00000000f0f0b3f4
>> TL=0002 TT=0010 TPC=00000000f0f0b3f4 TNPC=00000000f0f0b3f8
>> TL=0001 TT=0010 TPC=00000000f0f0a42c TNPC=00000000f0f0a430
>> **********************************************
>>
>> **********************************************
>> PSTATE=0000000000000015 TBA=00000000f0000000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0004 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0003 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0002 TT=0010 TPC=00000000f0000204 TNPC=0000000114800200
>> TL=0001 TT=0010 TPC=00000000f0003a04 TNPC=00000000f0003a08
>> **********************************************
>>
>> **********************************************
>> PSTATE=0000000000000015 TBA=00000000f0000000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0004 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0003 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0002 TT=0010 TPC=00000000f0000204 TNPC=0000000114800200
>> TL=0001 TT=0010 TPC=00000000f0003a04 TNPC=00000000f0003a08
>> **********************************************
>>
>> **********************************************
>> PSTATE=0000000000000015 TBA=00000000f0000000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0004 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0003 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0002 TT=0010 TPC=00000000f0000204 TNPC=0000000114800200
>> TL=0001 TT=0010 TPC=00000000f0003a04 TNPC=00000000f0003a08
>> **********************************************
>>
>> **********************************************
>> PSTATE=0000000000000015 TBA=00000000f0000000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0004 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0003 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0002 TT=0010 TPC=00000000f0000204 TNPC=0000000114800200
>> TL=0001 TT=0010 TPC=00000000f0003a04 TNPC=00000000f0003a08
>> **********************************************
>>
>> **********************************************
>> PSTATE=0000000000000015 TBA=00000000f0000000 DCU
>> Control=0000000000000000
>> AFSR=0000000000000000 AFAR=ffffffffffffffb8 PIL=000000000000000f
>> I-SFSR=00000000000010a2 D-SFSR=000000000004002b D-SFAR=00000000000007ff
>> TL=0005 TT=0010 TPC=00000000f0004200 TNPC=00000000f0004204
>> TL=0|
>> lom>
>> LOM event: +0h33m5s host power off
>> lom>
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> I've seen the same on mine... turned out to be bad memory... It doesn't like mixed speeds and I think they got to be in matched pairs...
> I could be wrong tho !
>
> Cheers
>
> Craig B
>
>
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