packet drop with intel gigabit / marwell gigabit
Jin Guojun [VFFS]
g_jin at lbl.gov
Fri Mar 24 20:08:26 UTC 2006
Lucas Holt wrote:
> On Mar 24, 2006, at 8:12 AM, OxY wrote:
>> hi guys!
>> well, i changed my motherboard and CPU from the
>> asus a7v8x+amd 2000+ xp to
>> the abit be7 + p4 2.4 (533fsb) and the packet loss fell down from
>> 8% to 2%, but
>> still have loss...
>> loss coming when i have load.. i guess it decreased because of the
>> bigger resources.
>> still waiting for tipps, hints, everything :)
> I don't think you'll ever get down to 0% in your situation. I
> noticed in the initial post that you have
> net.inet.tcp.inflight.enable=1 set. On my home network, turning that
> off helped a great deal with samba traffic to my freebsd file server/
> router. It didn't seem to affect traffic to my webserver much, but
> its very low traffic. The problem with tuning on other people's
> settings is that each workload is different though.
Especially, when a user did not mention what network traffic condition
and system load
cause packet loss, it is difficult to get insight of the problem. So,
the other thing in getting
help in troubleshooting and performance tuning is to provide systematic
and more detailed
> There might not be a miracle hack to get this working how you want.
> I'm sure the new box is a bit better as I attempted some of the steps
> outlined by Jin on my two machines. (amd 2300+ w/ msi nforce2 512mb
> ram and P4 2.4ghz 1gb ram 533mhz fsb) The P4 system was faster on
> all my tests by quite a large margin.
Just curious, were all your tests I/O related? 2300+ should over perform
P4 2.4GHz in some
> I must admit, I didn't follow all of Jin's calculations.
I had quite sloppy email since I did not intend to involve detailed
hardware discussion, but...
For example, when I said that "cache design affects memory bandwidth
[x1]" is very vague.
It really means: "cache design affects memory copy speed (except DMA)."
Generally, if we talk access data between CPU and main memory, then
technically [x1] is right.
If we talk to entire system design, theoretically, [x1] is wrong.
I stand corrected for all such writing.
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