[patch] enable mdio port 1, remove phy mask hard coding

[Aleksandr Rybalko]

On Tue, 27 Mar 2012 22:44:54 -0700
Adrian Chadd <adrian at freebsd.org> wrote:

>> Hi all,
>> 
>> This patch does a few things:
>> 
>> * it adds mdio port 1 (from MAC1/arge1);
>> * it removes the hard-coded assumption that arge0/arge1 share the
>> same mdio bus, which I believe is only relevant for AR71xx;
>> * it removes phymask from the arge config;
>> * it introduces a new configuration parameter, "multiphy", which
>> binds the port to the fake phy. The existing code does this if
>> phymask has
>> >1 bit set. This makes it absolutely obvious.
>> 
>> Since ar724x CPUs have >1 MDIO bus, we have to do this work to
>> support the switch phys that ship with these things.
>> 
>> 
>> This now raises the issue of how to handle switch PHYs and normal
>> PHYs on alternate busses. For example, the PB47 reference board has
>> the PHY for arge1 hang off the only MDIO bus on the board (AR7161) -
>> which is MDIO 0.
>> 
>> It's about time we fixed this stuff. I want to push in the switch
>> code from juli/pat/ray/stb now.
>> 
>> 
>> adrian

Patch looks good to me, but I don't understand: why you use
sc->arge_mac_unit as argument to ARGE_MII_READ/ARGE_MII_WRITE, but not
assigned bus_space_tag and bus_space_handle?

If you make ARGE_MII_READ/ARGE_MII_WRITE as alias to
ARGE_READ/ARGE_WRITE, maybe with offset to MDIO regs, it will be more
clear.

Thanks.

WBW
-- 
Alexandr Rybalko <ray at dlink.ua> 
aka Alex RAY <ray at ddteam.net>