Kernel Optimizations for Processors

[Damian Gerow]

Thus spake admin at forkthepenguin.com (admin at forkthepenguin.com) [28/12/03 00:16]:
> Is there a method for determining what options can be incorporated for a
> specific processor? The unit in question is a VIA C3 Samuel2 processor
> running at 800 Mhz. I've found many clues that this uses Cyrix
> instructions although the chipset uses the Centaur core. This is supposed
> to be an i686, but I've seen some issues on a Linux system with the same
> processor that required the kernel to be built with i586.

There's been a number of discussions about this over the past few months.
Take a quick peak through the archives.

In short: the GCC folk (at least for 2.95.x) assume that a 686-compatible
chip understands CMOV.  *Some* of the C3 cores understand it, others do not.
I was under the impression that the Samuel2 /did/ understand it.
Understanding CMOV is not a requirement for 686.

I know for a fact that the Ezra and Ezra-T chips (what I'm using) do *not*
understand CMOV.

I think you get ever-so-slightly better performance if you set your ARCH to
k6-2, though I use mine as i586/mmx.  As for the kernel configuration, I
left mine at I686_CPU, as the C3 /is/ a 686-class CPU.

I think the history of the C3 is that VIA bought out Cyrix and Centaur, and
brought both of them together.  Technically, the chip is Cyrix at its core,
I *believe*.  Correct me if I'm wrong.  The newer chips (Nehemiah and on)
are probably different.

> # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).

This is a 686-class CPU, not a 586-class CPU.

> # CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
> # mapped mode.  Default is 2-way set associative mode.

Again -- 486 vs. 686.

> # CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
> # of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
> # Otherwise, the NO_LOCK bit of CCR1 is cleared.  (NOTE 3)

Never used it.

> # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
> # reorder).  This option should not be used if you use memory mapped
> # I/O device(s).

Never used it.

> # CPU_IORT defines I/O clock delay time (NOTE 1).  Default values of
> # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
> # (no clock delay).

Never used it.

> # CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).

586 vs. 686.

> # CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
> # K5/K6/K6-2 cpus.

Used it, never bothered to see if it made a difference.

> # CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
> # flush at hold state.

Never used it -- 486 vs. 686.

> # CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
> # without cache flush at hold state, and (2) write-back CPU cache on
> # Cyrix 6x86 whose revision < 2.7 (NOTE 2).

Used it, never bothered to see if it made a difference.

> # NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
> # Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
> # executed.  This option is only needed if I586_CPU is also defined,
> # and should be included for any non-Pentium CPU that defines it.

'and ONLY Pentiums'

> Copyright (c) 1992-2003 The FreeBSD Project.
> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
>         The Regents of the University of California. All rights reserved.
> FreeBSD 4.9-RELEASE #0: Mon Oct 27 17:51:09 GMT 2003
>     root at freebsd-stable.sentex.ca:/usr/obj/usr/src/sys/GENERIC
> Timecounter "i8254"  frequency 1193182 Hz
> CPU: VIA C3 Samuel 2 (801.82-MHz 686-class CPU)
>   Origin = "CentaurHauls"  Id = 0x673  Stepping = 3
>   Features=0x803035<FPU,DE,TSC,MSR,MTRR,PGE,MMX>

Well, I guess the Samuel2 doesn't understand CMOV either.  Maybe it was the
Samuel that did...?  Dunno.  The Nehemiah does, though.