Kernel Optimizations for Processors

[admin at forkthepenguin.com]

Is there a method for determining what options can be incorporated for a
specific processor? The unit in question is a VIA C3 Samuel2 processor
running at 800 Mhz. I've found many clues that this uses Cyrix
instructions although the chipset uses the Centaur core. This is supposed
to be an i686, but I've seen some issues on a Linux system with the same
processor that required the kernel to be built with i586.

I see several options in LINT (below) that look like they might be
applicable, my goal is to optimize this system as much as possible. I
understand I can remove the following (in theory) from the kernel
configuration for a gain in performance :

cpu             I386_CPU
cpu             I486_CPU
cpu             I586_CPU

Below are some options selected from the LINT file. Can anyone provide any
clues as to which of these are applicable to my processor, and how I might
have been able to determine this myself? Or a more appropriate list
to have posted this to? dmesg snippet provided below.

Chris

# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
#
# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
# mapped mode.  Default is 2-way set associative mode.
#
# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
# Otherwise, the NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
#
# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
# reorder).  This option should not be used if you use memory mapped
# I/O device(s).
#
# CPU_ENABLE_SSE enables SSE/MMX2 instructions support.
#
# CPU_IORT defines I/O clock delay time (NOTE 1).  Default values of
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
# K5/K6/K6-2 cpus.
#
# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
# flush at hold state.
#
# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
# without cache flush at hold state, and (2) write-back CPU cache on
# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
#
# NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
# Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
# executed.  This option is only needed if I586_CPU is also defined,
# and should be included for any non-Pentium CPU that defines it.


Copyright (c) 1992-2003 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD 4.9-RELEASE #0: Mon Oct 27 17:51:09 GMT 2003
    root at freebsd-stable.sentex.ca:/usr/obj/usr/src/sys/GENERIC
Timecounter "i8254"  frequency 1193182 Hz
CPU: VIA C3 Samuel 2 (801.82-MHz 686-class CPU)
  Origin = "CentaurHauls"  Id = 0x673  Stepping = 3
  Features=0x803035<FPU,DE,TSC,MSR,MTRR,PGE,MMX>