instability of timekeeping

[Konstantin Belousov]

On Thu, Oct 29, 2015 at 12:56:38PM +0200, Andriy Gapon wrote:
> On 28/10/2015 18:47, Andriy Gapon wrote:
> > In either case I am going to add a few more trace points in et_start and the
> > HPET timer code and see if I can catch anything interesting there.
> 
> Okay, more data:
> https://people.freebsd.org/~avg/timekeeping-ktr.2.patch
> https://people.freebsd.org/~avg/timekeeping.2.ktrdump.txt
> 
> I think that the snippet (amended with some notes of mine) makes it painfully
> obvious that the timer interrupt got very delayed when all CPUs entered the idle
> state.
> I do not see anything that could suggest a FreeBSD bug.
> 
> There is another sad discovery.  Turns out that my CPU model provides two ways
> of doing C1E magic.  The sane one: the north bridge logic in the CPU performs a
> read of a configured LVL3 register so that C3 is entered.  The insane one: the
> CPU NB performs a write of a configured value to a configured SMI register, so
> that the SMI is generated and an SMM handler does the job (probably reading from
> LVL2 or LVL3).  Looking at MSR C001_0055 I see that my BIOS has chosen the
> insane approach[*], quite unfortunately.  Bugs in the SMM code are not unheard
> of, to put it mildly, so that could be an explanation for my problem.
> 
> So, I guess I'll just disable C1E and end this investigation.
> 
> [*]
> $ cpucontrol -m 0xc0010055 /dev/cpuctl0
> 
> 
> MSR 0xc0010055: 0x00000000 0x083400b0
> 
> SmiOnCmpHalt: SMI on chip multi-processing halt.
>  - write 0x34 to port 0xb0

What if you enable C3 (in OS, and possibly BIOS), but disable C1E ?
Does the issue with jitter persist ?