UART frequency drift

[Phil Spuhler]

Hi,
I have a question regarding your documentation on the UART. It says that 
the frequency drift on the asynchronous clocks can be up to 10% total. 
Shouldn't this be 5%? My reasoning on this is that if the bits are 
sampled in the center, the total frequency offset can be high enough to 
shift the sampling to the edge of the bit in 10 samples --> 50% shift / 
10 samples = 5%.
Cheers,
-Phil