re(4) problem
Daniel Gerzo
danger at FreeBSD.org
Mon Mar 10 08:55:10 PDT 2008
Hello Pyun,
> Since you're using MSI, would you try attached patch?
> Sorry, I don't have PCIe based hardware and RealTek's datasheet for
> PCIe variants is too poor to get useful information.
>
> --
> Regards,
> Pyun YongHyeon
Thank you for your quick reply, I will test your patch ASAP, but I have one
simple question:
Should I apply this patch on top of http://people.freebsd.org/~yongari/re/re.HEAD.patch
or what is this patch aginst?
Thank you.
> --- sys/dev/re/if_re.c.orig 2008-03-03 13:15:07.000000000 +0900
> +++ sys/dev/re/if_re.c 2008-03-10 19:42:50.000000000 +0900
> @@ -991,7 +991,7 @@
> * Allocate the parent bus DMA tag appropriate for PCI.
> */
> error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
> - BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
> + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
> BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
> NULL, NULL, &sc->rl_parent_tag);
> if (error) {
> @@ -1141,6 +1141,7 @@
> u_int16_t re_did = 0;
> int error = 0, rid, i;
> int msic, reg;
> + uint8_t cfg;
>
> sc = device_get_softc(dev);
> sc->rl_dev = dev;
> @@ -1182,6 +1183,13 @@
> } else
> pci_release_msi(dev);
> }
> + if (sc->rl_msi != 0) {
> + /* Enable config register write. */
> + CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
> + cfg = CSR_READ_1(sc, RL_CFG2);
> + CSR_WRITE_1(sc, RL_CFG2, cfg | RL_CFG2_MSI);
> + CSR_WRITE_1(sc, RL_EECMD, 0);
> + }
> }
>
> /* Allocate interrupt */
> @@ -2410,6 +2418,7 @@
> struct ifnet *ifp = sc->rl_ifp;
> struct mii_data *mii;
> u_int32_t rxcfg = 0;
> + uint16_t cfg;
> union {
> uint32_t align_dummy;
> u_char eaddr[ETHER_ADDR_LEN];
> @@ -2429,9 +2438,13 @@
> * RX checksum offload. We must configure the C+ register
> * before all others.
> */
> - CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
> - RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
> - RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
> + cfg = RL_CPLUSCMD_PCI_MRW;
> + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
> + cfg |= RL_CPLUSCMD_RXCSUM_ENB;
> + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
> + cfg |= RL_CPLUSCMD_VLANSTRIP;
> + CSR_WRITE_2(sc, RL_CPLUS_CMD,
> + cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB);
>
> /*
> * Init our MAC address. Even though the chipset
> --- sys/pci/if_rlreg.h.orig 2008-03-03 12:41:06.000000000 +0900
> +++ sys/pci/if_rlreg.h 2008-03-10 19:36:43.000000000 +0900
> @@ -382,6 +382,7 @@
> #define RL_CFG2_PCI66MHZ 0x01
> #define RL_CFG2_PCI64BIT 0x08
> #define RL_CFG2_AUXPWR 0x10
> +#define RL_CFG2_MSI 0x20
>
> /*
> * Config 3 register
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