re(4) problem

[Pyun YongHyeon]

On Mon, Mar 10, 2008 at 09:39:36AM +0100, Daniel Gerzo wrote:
 > Hello Pyun,
 > 
 > Monday, March 10, 2008, 2:55:26 AM, you wrote:
 > 
 > > On Sat, Mar 08, 2008 at 05:07:10PM +0100, Daniel Gerzo wrote:
 >  >> Hello,
 >  >> 
 >  >> Saturday, March 8, 2008, 12:11:03 AM, has been written:
 >  >> 
 >  >> > Hello Pyun,
 >  >> 
 >  >> > Friday, March 7, 2008, 5:38:15 AM, you wrote:
 >  >> 
 >  >> >> I guess your issue is not related with bus_dma fixes but improper
 >  >> >> handling of link state. Try attached patch and let me know how it
 >  >> >> goes.
 >  >> 
 >  >> > The attached patch didn't help, the box is again in the same status.
 >  >> > Can I provide you with some more detailed debugging info, or do you
 >  >> > have some other ideas what could be fixed?
 >  >> 
 >  >> > I could probably manage a remote access to that box, but no remote
 >  >> > console is available, and I don't know exactly how to trigger this
 >  >> > scenario, but I think it depends on the amount of traffic being sent
 >  >> > over the device.
 >  >> 
 >  >> If I won't hear from anybody in next 24 hours, I will have to replace
 >  >> the network device in this box, in order to get it running properly.
 >  >> 
 >  >> However, I don't consider this step as a right solution and I would
 >  >> rather better like to have it fixed in the driver.
 >  >> 
 > 
 > > Yes, I'd like to.
 > > By any chance, does the system have more than 4GB memory?
 > 
 > Well it does have exactly 4GB. Attached, I am sending you the output
 > of dmesg, pciconf and dmidecode utilities.
 > 
 > The machine has been rebooted yesterday, but I haven't replaced (well
 > re(4) is an onboard interface so better term would be disabled) the
 > given NIC, but at the moment, it works fine. I suppose it will stop
 > working in next 24 hours...
 > 

Since you're using MSI, would you try attached patch?
Sorry, I don't have PCIe based hardware and RealTek's datasheet for
PCIe variants is too poor to get useful information.

-- 
Regards,
Pyun YongHyeon
-------------- next part --------------
--- sys/dev/re/if_re.c.orig	2008-03-03 13:15:07.000000000 +0900
+++ sys/dev/re/if_re.c	2008-03-10 19:42:50.000000000 +0900
@@ -991,7 +991,7 @@
 	 * Allocate the parent bus DMA tag appropriate for PCI.
 	 */
 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
-	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
 	    NULL, NULL, &sc->rl_parent_tag);
 	if (error) {
@@ -1141,6 +1141,7 @@
 	u_int16_t		re_did = 0;
 	int			error = 0, rid, i;
 	int			msic, reg;
+	uint8_t			cfg;
 
 	sc = device_get_softc(dev);
 	sc->rl_dev = dev;
@@ -1182,6 +1183,13 @@
 			} else
 				pci_release_msi(dev);
 		}
+		if (sc->rl_msi != 0) {
+			/* Enable config register write. */
+			CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
+			cfg = CSR_READ_1(sc, RL_CFG2);
+			CSR_WRITE_1(sc, RL_CFG2, cfg | RL_CFG2_MSI);
+			CSR_WRITE_1(sc, RL_EECMD, 0);
+		}
 	}
 
 	/* Allocate interrupt */
@@ -2410,6 +2418,7 @@
 	struct ifnet		*ifp = sc->rl_ifp;
 	struct mii_data		*mii;
 	u_int32_t		rxcfg = 0;
+	uint16_t		cfg;
 	union {
 		uint32_t align_dummy;
 		u_char eaddr[ETHER_ADDR_LEN];
@@ -2429,9 +2438,13 @@
 	 * RX checksum offload. We must configure the C+ register
 	 * before all others.
 	 */
-	CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
-	    RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
-	    RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
+	cfg = RL_CPLUSCMD_PCI_MRW;
+	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
+		cfg |= RL_CPLUSCMD_RXCSUM_ENB;
+	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
+		cfg |= RL_CPLUSCMD_VLANSTRIP;
+	CSR_WRITE_2(sc, RL_CPLUS_CMD,
+	    cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB);
 
 	/*
 	 * Init our MAC address.  Even though the chipset
--- sys/pci/if_rlreg.h.orig	2008-03-03 12:41:06.000000000 +0900
+++ sys/pci/if_rlreg.h	2008-03-10 19:36:43.000000000 +0900
@@ -382,6 +382,7 @@
 #define	RL_CFG2_PCI66MHZ	0x01
 #define	RL_CFG2_PCI64BIT	0x08
 #define	RL_CFG2_AUXPWR		0x10
+#define	RL_CFG2_MSI		0x20
 
 /*
  * Config 3 register