Topology aware scheduling algorithm.

David Xu davidxu at
Tue Feb 26 11:52:13 UTC 2008

Jeff Roberson wrote:
> On Tue, 26 Feb 2008, David Xu wrote:
>> Jeff Roberson wrote:
>>> I think our identcpu.c already detects this information.  That's what 
>>> I'm using.  Although I assume that all cpus are identical and fall 
>>> back on a flat topology if this isn't the case.  I'd like to start 
>>> including more cache information though.
>>> Jeff
>> The patch does not assume all cpus are identical, in theory, one can 
>> have a machine with one cpu is 4-core and another is 2-core cpu.
>> only one place needs to be fixed in the patch,the global variable
>> cpu_feature, which is easy to fix for the patch.
>                         cpuid_count(4, cache_level, regs);
>             if ((regs[0] & 0x1f) == 0)
>                 break;
>             threads_per_cache = ((regs[0] & 0x3ffc000) >> 14) + 1;
> Does this work on all intel/amd cpus?
I can not find similar functions in amd's document.

however they seems to have updated the document for their new cpu
which sharing L3. The extended function 0x80000006 now reports L3
information in register %edx. They have never shared L2, so you can 
assume when the %edx is nonzero, it is now a cache-shared cpu, otherwise
cpus on same package just use crossbar to communicate with each other,
it is still better than old front-bus, scheduler may think about this
performance improvement.

> Thanks,
> Jeff

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