4.7 vs 5.2.1 SMP/UP bridging performance
Andrew Gallatin
gallatin at cs.duke.edu
Thu May 6 07:15:54 PDT 2004
Don Bowman writes:
>
> On the P4, there are mfence,lfence,sfence instructions to enforce
> memory ordering. These are cheaper than "lock; andl" or "cpuid",
> which are the traditional 'sync' instructions.
For what its worth, using those operations yeilds these results
on my 2.53GHz P4 (for UP)
Mutex (atomic_store_rel_int) cycles per iteration: 208
Mutex (sfence) cycles per iteration: 85
Mutex (lfence) cycles per iteration: 63
Mutex (mfence) cycles per iteration: 169
Mutex (none) cycles per iteration: 18
lfence looks like a winner..
Drew
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