STI, HLT in acpi_cpu_idle_c1

Don Bowman don at
Thu Jun 17 19:32:16 GMT 2004

in the intel instruction manual, the effect
of STI is that interrupts are enabled
*after* the next instruction.



the return is still run with interrupts disabled
(if they were prior to the STI).

In acpi_cpu_idle_c1, it does:


shouldn't there be a NOP in there so that interrupts
are guaranteed on?

We have traced down a lockup of the system with
a TAP emulator, and found that three processors
are in acpi_cpu_idle with bit 9 of EFLAGS clear,
indicating interrupts are disabled. The fourth
processor is spinning with nothing to do (since
hardclock etc don't come to it).

Suggestions? Am i off base on the sti/hlt? Is
there another problem that i might be running into?


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