cvs commit: src/sys/i386/cpufreq est.c

[John Baldwin]

On Monday 25 August 2008 04:21:42 pm Dimitry Andric wrote:
> On 2008-08-25 21:27, Renato Botelho wrote:
> > cpu0: <ACPI CPU> on acpi0
> > est0: <Enhanced SpeedStep Frequency Control> on cpu0
> > est0: Guessed bus clock (high) of 200 MHz
> > 
> > Fatal trap 18: integer divide fault while in kernel mode
> > cpuid = 0; acpi id = 00
> > ...
> > panic: integer divide fault
> 
> Unfortunately, there are CPU models around that have MSR_PERF_STATUS
> bits that are inconsistent, e.g:
> 
> - The low and high multipliers (bits 31:24 and 15:8) are equal, so if
>   you subtract them and then divide... boom :) 
> - Either the low or high multipliers (or both) are zero, which is also
>   not good, at least not with the current code.

This latter is what is probably the problem.  I think I will make this feature 
just be off by default and people can enable it with a tunable if it helps on 
their system.

-- 
John Baldwin