cvs commit: src/sys/i386/cpufreq est.c

Dimitry Andric dimitry at
Mon Aug 25 20:21:43 UTC 2008

On 2008-08-25 21:27, Renato Botelho wrote:
> cpu0: <ACPI CPU> on acpi0
> est0: <Enhanced SpeedStep Frequency Control> on cpu0
> est0: Guessed bus clock (high) of 200 MHz
> Fatal trap 18: integer divide fault while in kernel mode
> cpuid = 0; acpi id = 00
> ...
> panic: integer divide fault

Unfortunately, there are CPU models around that have MSR_PERF_STATUS
bits that are inconsistent, e.g:

- The low and high multipliers (bits 31:24 and 15:8) are equal, so if
  you subtract them and then divide... boom :) 
- Either the low or high multipliers (or both) are zero, which is also
  not good, at least not with the current code.

As an example, I originally added some multiplier sanity checks here:

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