Data Overruns while WRITING in Ultra Wide Transfers in AHC2940

[Justin T. Gibbs]

> Hi,
> 
> Setup:
> ---------
> I have ported the FreeBSD Aic7xxx driver to a proprietary OS. The OS runs on
> a MP box and has the AHC2940U card programmed in Target Mode.

...

> Problem Description:
> ----------------------------
> 1) All reads go thru properly.
> 2) All WRITES cause DATA OVERRUN to occur on the INITIATOR SIDE

Not all initiator reads, but all odd-length initiator reads.  This
is due to a bug in the FreeBSD OSM:

			/*
                         * If the transfer is of an odd length and in the
                         * "in" direction (scsi->HostBus), then it may
                         * trigger a bug in the 'WideODD' feature of
                         * non-Ultra2 chips.  Force the total data-length
                         * to be even by adding an extra, 1 byte, SG,   
                         * element.  We do this even if we are not currently 
                         * negotiated wide as negotiation could occur before 
                         * this command is executed.
                         */
                        if ((ahc->bugs & AHC_TMODE_WIDEODD_BUG) != 0
                         && (ccb->csio.dxfer_len & 0x1) != 0
                         && (ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
                                                                 ^^^^^^^^^^

Should read CAM_DIR_OUT.  The CAM data direction is always relative to
the intiator, and this workaround should only go into effect when we
are receiving data from the initiator.

--
Justin