[Bug 265974] SMR has several missing barriers

From: <bugzilla-noreply_at_freebsd.org>
Date: Fri, 26 Aug 2022 16:38:47 UTC

--- Comment #5 from Mark Johnston <markj@FreeBSD.org> ---
(In reply to Konstantin Belousov from comment #3)
> That said, atomic_add_acq on x86 has the sequentially consistent semantic
already (which is why you said that it works on Intel, right?).  So the
#ifdef from the patch in smr_enter() is not needed, use seq_cst fence
for all arches.

The ifdef makes some sense as an optimization.  On x86 we can combine the store
and barrier into one instruction, so why not do that?

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