git: 80d32a6b1d73 - main - hwpstate_amd(4): CPPC: Switch the default to maximum performance

The branch main has been updated by olce:

URL: https://cgit.FreeBSD.org/src/commit/?id=80d32a6b1d73e0c81303417fa280ac74ef1f417a

commit 80d32a6b1d73e0c81303417fa280ac74ef1f417a
Author:     Olivier Certner <olce@FreeBSD.org>
AuthorDate: 2026-02-09 17:45:07 +0000
Commit:     Olivier Certner <olce@FreeBSD.org>
CommitDate: 2026-02-20 10:12:53 +0000

    hwpstate_amd(4): CPPC: Switch the default to maximum performance
    
    Set controls to maximum performance to avoid regressions now that CPPC
    is activated by default and to match what the P-state support does.
    
    Relnotes:       yes
    Sponsored by:   The FreeBSD Foundation
    Differential Revision:  https://reviews.freebsd.org/D55253
---
 sys/x86/cpufreq/hwpstate_amd.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c
index 72fe6dbf6014..a1586f58166a 100644
--- a/sys/x86/cpufreq/hwpstate_amd.c
+++ b/sys/x86/cpufreq/hwpstate_amd.c
@@ -798,14 +798,6 @@ enable_cppc_cb(void *args)
 	data->init_request = sc->cppc.request;
 
 	data->request = sc->cppc.request;
-	/*
-	 * In Intel's reference manual, the default value of EPP is 0x80u which
-	 * is the balanced mode. For consistency, we set the same value in AMD's
-	 * CPPC driver.
-	 */
-	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0x80);
-	/* Enable autonomous mode by setting desired performance to 0. */
-	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0);
 	/*
 	 * Assuming reading MSR_AMD_CPPC_CAPS_1 succeeded, if it stays at its
 	 * reset value (0) before CPPC activation (not supposed to happen, but
@@ -834,6 +826,16 @@ enable_cppc_cb(void *args)
 	    lowest_perf);
 	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_MAX_PERF_BITS,
 	    highest_perf);
+	/*
+	 * Set controls to maximum performance to avoid regressions now that
+	 * CPPC is activated by default and to match what the P-state support
+	 * does.
+	 */
+	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0);
+	/* 0 in "Desired Performance" is autonomous mode. */
+	MPASS(highest_perf != 0);
+	SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS,
+	    highest_perf);
 
 	error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, data->request);
 	if (error != 0)