git: cca0d3bbd8c9 - main - amdsbwd: always enable watchdog register decoding
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Date: Mon, 13 Dec 2021 11:37:14 UTC
The branch main has been updated by avg: URL: https://cgit.FreeBSD.org/src/commit/?id=cca0d3bbd8c9f8b50c6940c33704a6c8c464b68f commit cca0d3bbd8c9f8b50c6940c33704a6c8c464b68f Author: Andriy Gapon <avg@FreeBSD.org> AuthorDate: 2020-05-27 10:15:54 +0000 Commit: Andriy Gapon <avg@FreeBSD.org> CommitDate: 2021-12-13 11:36:50 +0000 amdsbwd: always enable watchdog register decoding This seems to be required even if the watchdog is accessed via the common MMIO space. Tested on: - Ryzen 3 3200U APU; - Ryzen 7 5800X CPU with X570 chipset. MFC after: 2 weeks --- sys/dev/amdsbwd/amdsbwd.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/sys/dev/amdsbwd/amdsbwd.c b/sys/dev/amdsbwd/amdsbwd.c index 452b014d2240..a7ab67f1a8b8 100644 --- a/sys/dev/amdsbwd/amdsbwd.c +++ b/sys/dev/amdsbwd/amdsbwd.c @@ -381,24 +381,23 @@ amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) uint8_t val; char buf[36]; + /* + * Enable decoding of watchdog MMIO address. + */ + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); + val |= AMDFCH41_WDT_EN; + pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); +#ifdef AMDSBWD_DEBUG + val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); + device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val); +#endif + val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); if ((val & AMDFCH41_MMIO_EN) != 0) { /* Fixed offset for the watchdog within ACPI MMIO range. */ amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; } else { - /* - * Enable decoding of watchdog MMIO address. - */ - val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); - val |= AMDFCH41_WDT_EN; - pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); -#ifdef AMDSBWD_DEBUG - val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); - device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", - val); -#endif - /* Special fixed MMIO range for the watchdog. */ *addr = AMDFCH41_WDT_FIXED_ADDR; }