PERFORCE change 32454 for review
Juli Mallett
jmallett at FreeBSD.org
Mon Jun 2 22:34:15 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=32454
Change 32454 by jmallett at jmallett_dalek on 2003/06/02 22:33:44
Clean, new PTE header which describes things simply from a
64-bit point of view, suitable for use with simple MMU
management code.
Affected files ...
.. //depot/projects/mips/sys/mips/include/pte.h#5 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/pte.h#5 (text+ko) ====
@@ -1,266 +1,121 @@
-/* $NetBSD: pte.h,v 1.13 2002/10/14 05:11:23 chs Exp $ */
-/* $NetBSD: mips3_pte.h,v 1.15 2002/06/24 05:46:47 simonb Exp $ */
-
/*-
- * Copyright (c) 1997 The NetBSD Foundation, Inc.
- * All rights reserved.
+ * Author: Juli Mallett <jmallett at FreeBSD.org>
+ * Date: June 02, 2003
+ * Description:
+ * Header describing page table entries and the TLB of the MIPS.
*
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
- * NASA Ames Research Center.
+ * This file is in the public domain.
*
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * $FreeBSD$
*/
-/*
- * Copyright 1996 The Board of Trustees of The Leland Stanford
- * Junior University. All Rights Reserved.
- *
- * Permission to use, copy, modify, and distribute this
- * software and its documentation for any purpose and without
- * fee is hereby granted, provided that the above copyright
- * notice appear in all copies. Stanford University
- * makes no representations about the suitability of this
- * software for any purpose. It is provided "as is" without
- * express or implied warranty.
- */
-/*
- * Copyright (c) 1988 University of Utah.
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * the Systems Programming Group of the University of Utah Computer
- * Science Department and Ralph Campbell.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * from: Utah Hdr: pte.h 1.11 89/09/03
- *
- * from: @(#)pte.h 8.1 (Berkeley) 6/10/93
- */
-
-#ifndef __MIPS_PTE_H__
-#define __MIPS_PTE_H__
+#ifndef _MACHINE_PTE_H_
+#define _MACHINE_PTE_H_
/*
- * R4000 hardware page table entry
+ * 64-bit PTE.
*/
-
-#ifndef LOCORE
-#if 0/*DOCUMENTATION&OLD*/
-struct mips3_pte {
-#if BYTE_ORDER == BIG_ENDIAN
-unsigned int pg_prot:3, /* SW: access control */
- pg_pfnum:23, /* HW: core page frame number or 0 */
- pg_attr:3, /* HW: cache attribute */
- pg_m:1, /* HW: dirty bit */
- pg_v:1, /* HW: valid bit */
- pg_g:1; /* HW: ignore asid bit */
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
-unsigned int pg_g:1, /* HW: ignore asid bit */
- pg_v:1, /* HW: valid bit */
- pg_m:1, /* HW: dirty bit */
- pg_attr:3, /* HW: cache attribute */
- pg_pfnum:23, /* HW: core page frame number or 0 */
- pg_prot:3; /* SW: access control */
+#ifndef LOCORE
+typedef unsigned long pt_entry_t;
+#else
+#define PTESIZE 64
#endif
-};
-#endif
+#ifndef LOCORE
/*
- * Structure defining an tlb entry data set.
+ * Structure defining the whole of the TLB.
+ * XXX This is for NetBSD compat, and I really want to move away from
+ * this sort of thing. Badly.
*/
-
struct tlb {
- int tlb_mask;
- int tlb_hi; /* XXX should be 64 bits */
- int tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */
- int tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */
+ uint32_t tlb_mask; /* PageMask */
+ uint32_t tlb_padding; /* alignment :( */
+ register_t tlb_hi; /* EntryHi */
+ register_t tlb_lo0; /* EntryLo0 */
+ register_t tlb_lo1; /* EntryLo1 */
};
#endif /* LOCORE */
-#define MIPS3_PG_WIRED 0x80000000 /* SW */
-#define MIPS3_PG_RO 0x40000000 /* SW */
-#define MIPS3_PG_M 0x20000000 /* SW */
+/*
+ * TLB and PTE management. Most things operate within the context of
+ * EntryLo0,1. Things which work with EntryHi have a HI in their name
+ * somewhere obvious: usually after PG_ or MIPS_.
+ */
-#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
-#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
-#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
-#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
-#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
-#define MIPS3_PG_V 0x00000002 /* Valid */
-#define MIPS3_PG_NV 0x00000000
-#define MIPS3_PG_D 0x00000004 /* Dirty */
-#define MIPS3_PG_ATTR 0x0000003f
+/*
+ * PFN for EntryLo register. Upper bits are 0, which is to say that
+ * bit 29 is the last hardware bit; Bits 30 and upwards (EntryLo is
+ * 64 bit though it can be referred to in 32-bits providing 2 software
+ * bits safely. We use it as 64 bits to get many software bits, and
+ * god knows what else.) are unacknowledged by hardware. They may be
+ * written as anything, but otherwise they have as much meaning as
+ * other 0 fields.
+ *
+ * Given this, we just shift the PA right a little.
+ */
+#define MIPS_TLB_SWSHIFT 30
+#define MIPS_PFN_SHIFT 6
+#define MIPS_PFN_MASK 0x3FFFFFC0
+#define MIPS_PA_TO_PFN(pa) ((pa) >> MIPS_PFN_SHIFT)
+#define MIPS_PFN_TO_PA(pfn) ((pfn) << MIPS_PFN_SHIFT)
+#define MIPS_PTE_TO_PFN(pte) ((pte) & MIPS_PFN_MASK)
+#define MIPS_PTE_TO_PA(pte) (MIPS_PFN_TO_PA(MIPS_PTE_TO_PFN((pte))))
-#define MIPS3_CCA_TO_PG(cca) ((cca) << 3)
+/*
+ * VPN for EntryHi register. Upper two bits select user, supervisor,
+ * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 to 13. From
+ * bit 12 to bit 8 there is a 5-bit 0 field. Low byte is ASID.
+ */
+#define MIPS_HI_R_SHIFT 62
+#define MIPS_HI_FILL_SHIFT 40
+#define MIPS_HI_VPN2_SHIFT 13
+#define MIPS_HI_VPN2_BMASK 0xFFFFFFE
+#define MIPS_HI_VPN2_MASK (MIPS_HI_VPN2_BMASK << MIPS_HI_VPN2_SHIFT)
+#define MIPS_HI_VA_TO_VPN2(va) (((va) & MIPS_HI_VPN2_BMASK) << MIPS_HI_VPN2_SHIFT)
-#define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2)
-#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */
-#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */
-#else /* HPCMIPS_L1CACHE_DISABLE */
-#define MIPS3_PG_CACHED mips3_pg_cached
-#define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3)
-#endif /* ! HPCMIPS_L1CACHE_DISABLE */
-#define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7)
-
-/* Write protected */
-#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
-
-/* Not wr-prot not clean */
-#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED)
-
-/* Not wr-prot but clean */
-#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
-#define MIPS3_PG_IOPAGE(cca) \
- (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca))
-#define MIPS3_PG_FRAME 0x3fffffc0
-#ifdef MIPS3_4100 /* VR4100 core */
-#define MIPS3_PG_SHIFT 4
-#else
-#define MIPS3_PG_SHIFT 6
-#endif
-
-/* pte accessor macros */
-
-#define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
-#define mips3_paddr_to_tlbpfn(x) \
- (((vm_paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
-#define mips3_tlbpfn_to_paddr(x) \
- ((vm_paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
-#define mips3_vad_to_vpn(x) ((vm_offset_t)(x) & MIPS3_PG_SVPN)
-#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
-
-#define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte))
-#define MIPS3_PAGE_IS_RDONLY(pte,va) \
- (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
-
-
-#define MIPS3_PG_SIZE_4K 0x00000000
-#define MIPS3_PG_SIZE_16K 0x00006000
-#define MIPS3_PG_SIZE_64K 0x0001e000
-#define MIPS3_PG_SIZE_256K 0x0007e000
-#define MIPS3_PG_SIZE_1M 0x001fe000
-#define MIPS3_PG_SIZE_4M 0x007fe000
-#define MIPS3_PG_SIZE_16M 0x01ffe000
-#define MIPS3_PG_SIZE_64M 0x07ffe000
-#define MIPS3_PG_SIZE_256M 0x1fffe000
-
-#define PG_ASID 0x000000ff /* Address space ID */
+/*
+ * TLB page bits that aren't really flags:
+ * ODDPG: Is this page odd? ! XXX NetBSD compat
+ * HVPN: Hardware VPN mask ! XXX NetBSD compat
+ * ASID: Address space ID
+ */
+#define PG_ODDPG 0x00001000
+#define PG_HVPN MIPS_HI_VPN2_MASK
+#define PG_ASID 0x000000ff
-#ifndef LOCORE
-#include <machine/cpu.h>
-
-typedef unsigned long pt_entry_t;
-#if 0
-typedef union pt_entry {
- unsigned int pt_entry; /* for copying, etc. */
- struct mips3_pte pt_mips3_pte;
-} pt_entry_t;
-#endif
-
-#define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */
-
-#define mips_pg_v(entry) ((entry) & MIPS3_PG_V)
-#define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED)
-
-#define mips_pg_m_bit() (MIPS3_PG_D)
-#define mips_pg_rw_bit() (MIPS3_PG_D)
-#define mips_pg_ro_bit() (MIPS3_PG_RO)
-#define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE)
-#define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE)
-#define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE)
-#define mips_pg_global_bit() (MIPS3_PG_G)
-#define mips_pg_wired_bit() (MIPS3_PG_WIRED)
-
-#define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte))
-#define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va))
-
-#define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vm_offset_t)(x))
-#define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x))
-
/*
- * Address of current address space page table maps
+ * TLB flags managed in hardware:
+ * C: We ignore this field, as it will only give us a
+ * headache in certain CPUs. Better not to bother for
+ * now, though in time we may want to support multiple
+ * cache schemes for VM.
+ * D: Dirty bit. This means a page is writable. It is not
+ * set at first, and a write is trapped, and the dirty
+ * bit is set. See also PG_RO.
+ * V: Valid bit. Obvious, isn't it?
+ * G: Global bit. This means that this mapping is present
+ * in EVERY address space, and to ignore the ASID when
+ * it is matched.
*/
-#ifdef _KERNEL
+#define PG_D 0x04
+#define PG_V 0x02
+#define PG_G 0x01
+
/*
- * PTmap is recursive pagemap at top of virtual address space.
- * Within PTmap, the lev1 and lev0 page tables can be found.
+ * VM flags managed in software:
+ * RO: Read only. Never set PG_D on this page, and don't
+ * listen to requests to write to it.
+ * W: Wired.
+ * M: Managed.
*/
- /* lev3 page tables */
-#define PTmap ((pt_entry_t*)VPTBASE)
- /* lev2 page tables */
-#define PTlev2 ((pt_entry_t*)(PTmap+(PTLEV1I<<MIPS_L2SHIFT)))
- /* lev1 page tables */
-#define PTlev1 ((pt_entry_t*)(PTlev2+(PTLEV1I<<MIPS_L2SHIFT)))
- /* pte that maps lev1 page table */
-#define PTlev1pte ((pt_entry_t*)(PTlev1+(PTLEV1I*sizeof(pt_entry_t))))
-#endif
+#define PG_RO (0x01 << MIPS_TLB_SWSHIFT)
+#define PG_W (0x02 << MIPS_TLB_SWSHIFT)
+#define PG_M (0x04 << MIPS_TLB_SWSHIFT)
-#ifdef _KERNEL
/*
- * virtual address to page table entry and
- * to physical address.
- * Note: this work recursively, thus vtopte of a pte will give
- * the corresponding lev1 that in turn maps it.
+ * Amalgamations of flags in software:
+ * PROT: Protection related software flags.
*/
-#define vtopte(va) (PTmap + (btop(va) \
- & ((1 << 3*MIPS_PTSHIFT)-1)))
-#endif /* _KERNEL */
+#define PG_PROT (PG_RO)
-#endif /* ! LOCORE */
-#endif /* __MIPS_PTE_H__ */
+#endif /* _MACHINE_PTE_H_ */
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