PERFORCE change 32453 for review
Juli Mallett
jmallett at FreeBSD.org
Mon Jun 2 22:32:12 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=32453
Change 32453 by jmallett at jmallett_dalek on 2003/06/02 22:32:06
Support for reading/writing 64-bit CP0 registers. Add use of
such for TLB.
Affected files ...
.. //depot/projects/mips/sys/mips/include/cpufunc.h#11 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/cpufunc.h#11 (text+ko) ====
@@ -39,6 +39,32 @@
__asm __volatile ("sync" : : : "memory");
}
+#define MIPS_RDRW64_COP0(n,r) \
+static __inline u_int64_t \
+mips_rd_ ## n (void) \
+{ \
+ int v0; \
+ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
+ : [v0] "=&r"(v0)); \
+ return (v0); \
+} \
+static __inline void \
+mips_wr_ ## n (u_int64_t a0) \
+{ \
+ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
+ __XSTRING(COP0_SYNC)";" \
+ "nop;" \
+ "nop;" \
+ : \
+ : [a0] "r"(a0)); \
+}
+
+MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0)
+MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1)
+MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI)
+
+#undef MIPS_RDRW64_COP0
+
#define MIPS_RDRW32_COP0(n,r) \
static __inline u_int32_t \
mips_rd_ ## n (void) \
@@ -66,6 +92,8 @@
MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE)
MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS)
+#undef MIPS_RDRW32_COP0
+
static __inline register_t
intr_disable(void)
{
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