8.1-RC2 MCE caused by some LAPIC/clock changes?

Andriy Gapon avg at icyb.net.ua
Wed Jul 21 09:17:17 UTC 2010

on 21/07/2010 11:33 Andriy Gapon said the following:
> Not sure how to interpret this properly.
> One possibility is a hardware problem where interrupt message route between
> ioapic2 and CPU to which lapic3 belongs is flaky.

Or, I/O path between that CPU and the PCI slot where the device resides.  Or the
CPU. Or...
I think that lapic2 and lapic3 reside in a different physical package/socket,
given that you have 2x2 CPU/core configuration.

BTW, John, could there be any problem because of this:
ioapic1: WARNING: intbase 48 != expected base 24
ioapic2: WARNING: intbase 56 != expected base 55
ioapic3: WARNING: intbase 24 != expected base 63

Andriy Gapon

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