BMAC Ethernet Driver

[Nathan Whitehorn]

Marcel Moolenaar wrote:
> 
> On Apr 2, 2008, at 8:07 PM, Nathan Whitehorn wrote:
> 
>>> "ofwdump -aP interrupts" gives:
>>>     ...
>>>       Node 0xff95fd30: escc
>>>         Node 0xff95ffb8: ch-a
>>>           interrupts:
>>>             00 00 00 16 00 00 00 01 00 00 00 05 00 00 00 00 00 00 00 06
>>>             00 00 00 00
>>>         Node 0xff960a08: ch-b
>>>           interrupts:
>>>             00 00 00 17 00 00 00 01 00 00 00 07 00 00 00 00 00 00 00 08
>>>             00 00 00 00
>>>     ...
>>>       Node 0xff970618: ata-4
>>>         interrupts:
>>>           00 00 00 13 00 00 00 01 00 00 00 0b 00 00 00 00
>>>         Node 0xff973358: disk
>>>
>>>
>>> Can you send me the output of ofwdump on your machine?
>>
>> So it looks like that corresponds to the OF output, to within the 
>> macio limit of 5 interrupts per device. Two of the interrupts for each 
>> channel (probably the first two after the main one) are the DBDMA 
>> interrupts for transmit and receive DMA on each UART. The others, I 
>> don't know. G4 machines seem to have a lot of 0 interrupts listed in 
>> OF. Maybe we should
>> remove them? I somehow doubt that 0 is a valid IRQ.
> 
> OpenPIC uses 2 cells per interrupt. The first being the interrupt line;
> the second being the interrupt trigger properties. As such, there are
> 3 interrupts per SCC channels and 2 for ATA:
>     SCC-A:    0x16, 0x05, 0x06
>     SCC-B:    0x17, 0x07, 0x08
>     ATA:    0x13, 0x0b
> 
> It seems that the DMA interrupts are edge triggered, so we can easily
> filter them out to preserve the old behaviour.

Ah, ok. I wan't aware OpenPIC behaved that way -- that explains the 0 
interrupts. I suppose as an alternative to filtering them out, you could 
make SCC use nintr/nchannels as the increment into the array of 
interrupts, instead of incrementing by one.

Since bm depends on those DBDMA interrupts, like any DBDMA device, we 
shouldn't filter them out globally, and I'm hesitant to add a bunch of 
SCC-specific hacks to macio. We will also need them if we want to 
support DMA on the onboard ATA controller or want to support the AWACS 
sound chip.

> I guess on your machine, interrupts use only 1 cell. This means we need
> to fix macio(4) to interpret the "#interrupt-cells" property of the
> interrupt controller in the "interrupt-parent" property...

So it would seem:
Node 0xff860a58: mac-io
   Node 0xff861220: interrupt-controller
     #interrupt-cells:
       00 00 00 01

This sounds like a good solution. Do you want to make the patch, or do 
you want me to give it a try?
-Nathan