BMAC Ethernet Driver

[Marcel Moolenaar]

On Apr 2, 2008, at 8:07 PM, Nathan Whitehorn wrote:

>> "ofwdump -aP interrupts" gives:
>> 	...
>>       Node 0xff95fd30: escc
>>         Node 0xff95ffb8: ch-a
>>           interrupts:
>>             00 00 00 16 00 00 00 01 00 00 00 05 00 00 00 00 00 00  
>> 00 06
>>             00 00 00 00
>>         Node 0xff960a08: ch-b
>>           interrupts:
>>             00 00 00 17 00 00 00 01 00 00 00 07 00 00 00 00 00 00  
>> 00 08
>>             00 00 00 00
>> 	...
>>       Node 0xff970618: ata-4
>>         interrupts:
>>           00 00 00 13 00 00 00 01 00 00 00 0b 00 00 00 00
>>         Node 0xff973358: disk
>>
>>
>> Can you send me the output of ofwdump on your machine?
>
> So it looks like that corresponds to the OF output, to within the  
> macio limit of 5 interrupts per device. Two of the interrupts for  
> each channel (probably the first two after the main one) are the  
> DBDMA interrupts for transmit and receive DMA on each UART. The  
> others, I don't know. G4 machines seem to have a lot of 0 interrupts  
> listed in OF. Maybe we should
> remove them? I somehow doubt that 0 is a valid IRQ.

OpenPIC uses 2 cells per interrupt. The first being the interrupt line;
the second being the interrupt trigger properties. As such, there are
3 interrupts per SCC channels and 2 for ATA:
	SCC-A:	0x16, 0x05, 0x06
	SCC-B:	0x17, 0x07, 0x08
	ATA:	0x13, 0x0b

It seems that the DMA interrupts are edge triggered, so we can easily
filter them out to preserve the old behaviour.

I guess on your machine, interrupts use only 1 cell. This means we need
to fix macio(4) to interpret the "#interrupt-cells" property of the
interrupt controller in the "interrupt-parent" property...

-- 
Marcel Moolenaar
xcllnt at mac.com