vm_fault when accessing PCI address space

[Damjan Marion]

On May 22, 2011, at 8:04 PM, Olivier Houchard wrote:

> On Sat, May 21, 2011 at 01:34:02AM +0200, Damjan Marion wrote:
>> 
>> Hi,
>> 
> 
> Hi Damjan,
> 
>> I'm made some progress on porting existing marvell orion ARM code 
>> to work on 88F5181L SoC which have embedded PCI controller.
>> 
>> PCI driver detects resources and recognizes Atheros wlan card, 
>> however when driver tries to access 1st register with
>> bus_space_write_4 vm_fault happens:
>> 
>> vm_fault(0xc0e4f000, e8007000, 2, 0) -> 1
>> Fatal kernel mode data abort: 'Translation Fault (S)'
>> trapframe: 0xc0d3faa4
>> FSR=00000005, FAR=e800704c, spsr=600000d3
>> r0 =00000000, r1 =e8000000, r2 =0000704c, r3 =00000003
>> r4 =c13cd000, r5 =c0c4bd60, r6 =c0bece04, r7 =c12dd000
>> r8 =00000023, r9 =c0d074c8, r10=c0d3fba4, r11=c0d3fb00
>> r12=00000000, ssp=c0d3faf0, slr=c095f830, pc =c0bece04
>> 
>> [ thread pid 0 tid 100000 ]
>> Stopped at      generic_bs_w_4: str     r3, [r1, r2]
>> 
>> 0xe8000000 is PCI mem space. I can see that PCI driver (mv_pci.c) allocates this resource:
>> 
>> pcib0: <Marvell Integrated PCI/PCI-E Controller> mem 0xf1030000-0xf1031fff irq 0 on fdtbus0
>> pci0: <PCI bus> on pcib0
>> mv_pcib_alloc_resource: start=0xe8000000 end=0xe800ffff count=0x00010000 flags=0x00
>> 
>> What can be the reason for this vm_fault? 
>> 
> 
> I don't know the Marvell, nor the FDT code, well, but you shouldn't access
> to the PCI mem space using the physical address, so maybe something is missing
> from the dts ?
> Also, reading the mv code, there's this in mv_machdep.c :
> 	if (fdt_pci_devmap(child, &fdt_devmap[i],
> 			    MV_PCIE_IO_BASE, MV_PCIE_MEM_BASE) != 0)
> 				return (ENXIO);
> but nothing equivalent for the PCI controller (as it seems the Orion has both
> PCI and PCIe). So maybe it is lacking ?

Hi Olivier,

yes, that code is wrong. It is inside loop so if there are 2 PCI adapters 
(i.e. PCIe + PCI) it will try to map both to same VA.

Also different Marvell SoCs are using different PCI regions, so this needs to be adjusted to work with my SoC.

Thanks,

Damjan