Memory barrier

[Leonardo Fogel]

On Thu, 10/8/15, John-Mark Gurney wrote:

> If this is a PCI device, you need to do a read from the device before
> it is guaranteed that all the bridges have flushed the writes to the
> device...  A barrier only guarantees from the processor's perspective
> that the write "has completed", but not that it will reach the device..
> 
> If this is a different bus, then the rules are probably different...

Good points. I've ignored them.
It is a System-on-Chip based on ARM, which has different buses and bridges. Device registers are memory-mapped (MMIO).
The formal definition of memory barriers is quite obscure; in simple terms: memory accesses before the barrier are "observed" before memory accesses after the barrier. However, the definition of an "observer" is not provided. Since the device registers are memory-mapped, I've assumed that a write before the barrier would reach the device before a write after the barrier. But, on a second thought, the buses and bridges might reorder them. I really don't know, but, to be on the safe side, I'll include the read.
Thanks for your attention.
Leonardo.