Memory barrier

[John-Mark Gurney]

Leonardo Fogel wrote this message on Sun, Sep 06, 2015 at 06:53 -0700:
> Please, what are the correct barriers for the following cases?
> 
> Case 1:
>    bus_write_1(region_0, ...);
>    /* barrier here */
>    DELAY(some_time);
> 
> Case 2:
>    bus_write_1(region_0, ...);
>    /* barrier here */
>    bus_write_1(region_2, ...);
> 
> In the first one, I want the write to reach the device before the thread busy-waits. As I understand it, bus_space_barrier(9) is not adequate, because it does not prevent the processor from executing instructions (or load/store to RAM) before the write completes.
> 
> In the second one, I want the write to a device (e.g. power management) to complete before the write to another starts/completes. Again, bus_space_barrier() seems not to be adequate because it can not cover two regions.
> 
> Thank you for your time.

If this is a PCI device, you need to do a read from the device before
it is guaranteed that all the bridges have flushed the writes to the
device...  A barrier only guarantees from the processor's perspective
that the write "has completed", but not that it will reach the device..

If this is a different bus, then the rules are probably different...

-- 
  John-Mark Gurney				Voice: +1 415 225 5579

     "All that I will do, has been done, All that I have, has not."