APIC/SMP on UP? (was Re: Load average with CURRENT)

[Jon Noack]

On 3/9/2004 10:17 AM, Justin Dossey wrote:
> On Tue, 9 Mar 2004, Conrad Sabatier wrote:
>>I've been meaning to ask about this.  Is there anything to be gained on a UP
>>box by enabling APIC and/or SMP?  I'm running on an Athlon here, with ULE:
>>
>>CPU: AMD Athlon(tm) Processor (998.07-MHz 686-class CPU)
>>  Origin = "AuthenticAMD"  Id = 0x622  Stepping = 2  Features=0x183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR>
>>  AMD Features=0xc0400000<AMIE,DSP,3DNow!>
> 
> I'd say yes, there is.  APIC reduces interrupt overhead and provides
> an on-chip timer. It also provides better interrupt sharing.

APIC, yes (see above).  SMP incurs a fairly significant amount of 
overhead (extra locking, etc.).  I think I heard something a while back 
about attempts to selectively enable SMP locking at runtime (so that 
leaving SMP enabled in GENERIC doesn't hurt so much for UP), but then 
again that might have been a dream... ;-)

In any case, this is what I run on my UP boxes:
#options	SMP		# Symmetric MultiProcessor Kernel
device		apic		# I/O APIC

Jon Noack