A RPi4 xHCI VL805 problem that needs to be avoided: "xhci: quirks: add link TRB quirk for VL805"

[Mark Millard]

On 2020-Oct-27, at 01:02, Hans Petter Selasky <hps at selasky.org> wrote:

> On 2020-10-27 00:58, Mark Millard via freebsd-arm wrote:
>> https://github.com/raspberrypi/linux/pull/3929 reports:
>> QUOTE
>> The VL805 controller can't cope with the TR Dequeue Pointer for an endpoint
>> being set to a Link TRB. The hardware-maintained endpoint context ends up
>> stuck at the address of the Link TRB, leading to erroneous ring expansion
>> events whenever the enqueue pointer wraps to the dequeue position.
>> If the search for the end of the current TD and ring cycle state lands on
>> a Link TRB, move to the next segment.
>> END QUOTE
>> Also: Dealing with the link trb also toggling the ring cycle state
>> is something to watch for according to the later notes.
> 
> Is this an issue under FreeBSD too? Can it be reproduced?
> 

I've no clue how to set up a test to see if FreeBSD can set the TR Dequeue
Pointer for an end point to a Link TRB vs. showing that it somehow avoids
doing that.

I reported it on just the basis of the claim that the controller mishandles
the condition if it occurs.

===
Mark Millard
marklmi at yahoo.com
( dsl-only.net went
away in early 2018-Mar)