Random number generator on rpi

Steve Kiernan stevek at juniper.net
Wed Jul 20 14:10:58 UTC 2016


On Wed, 20 Jul 2016 16:11:44 +0800
Jia-Shiun Li <jiashiun at gmail.com> wrote:

> On Mon, Jul 18, 2016 at 11:54 PM, Steve Kiernan <stevek at juniper.net> wrote:
> 
> >
> > You might want to see my RPi rng driver review up on Phabricator.
> > It is interrupt driven, which keeps the CPU utilization down to a fraction
> > of a percent, whereas using a callout or other method easily consumes much
> > more of the CPU.
> >
> > The review is here:
> > https://reviews.freebsd.org/D6888
> >
> > Note that for RBG (random bit generator) like the one in the RPi, they are
> > not really RNGs themselves but random bit sources that must be processed
> > by other algorithms to generate random numbers. So even if one were to grab
> > the data to test for "randomness", one would need to not assume the rndtest
> > would necessarily be appropriate, since the values returned by the RBG are
> > not to be used directly as random numbers without post-processing.
> >
> > -Steve
> >  
> 
> 
> I saw it committed yesterday. Great & thanks!
> 
> BTW does it have any other document other than
>   http://pastehtml.com/view/crkxyohmp.rtxt
> as mentioned in
>   https://www.raspberrypi.org/forums/viewtopic.php?f=29&t=19334&start=275 ?
> 
> I cannot find any other source of info other than linux source and the
> above link...

There's not a lot of information available, but I know from working on
other Broadcom SoCs that have the same register setup for the RBG, it
appears to be based on the RBG100 design. I validated the settings from
empirical testing and what I know about the RBG100.

For example, the BCM56340 enterprise switching SoC has the same RBG in
it, except the one on the RPi appears to have a smaller FIFO. On the
BCM56340, the FIFO threshold default value is number of 32-bit words,
while on the RPi it appears to be number of bytes, but everything else
is the same. On the RPi it fires the interrupt when the number of words
available in the status register only has 4 32-bit words, instead of 16
that is seen on the switching SoC version.

-Steve
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