Sandy Bridge Support for FBSD 8.1

[John Baldwin]

On Monday, November 14, 2011 4:35:33 pm John Veit wrote:
> 
> The Intel SandyBridge_EDS volume 2 decribes how the CPUBUS0, CPUBUS1 values 
are accessed for each physical CPU Slot. The BIOS loads these values at boot 
time. For SandyBridge each physical CPU has multiple PCI segments for 
integrated IO and CPU devices. Thus when 2 CPU's are present the following 
values are set:
> CPU0BUS0=0 (IIO, PCH), CPU0BUS1=63 (IMC, DMA, etc), 
> CPU1BUS0=64, CPU1BUS1=127.
> 
> Note: We are using amd64 build of FBSD 8.1. It looks like the qpi driver is 
not supported for Sandy Bridge.

Yeah, we'll have to fix qpi.c.  Let me see if I can find that manual tomorrow 
and come up with a fix for qpi.c.  I can test it on my desktop here which has 
SB.

Hmm, I can't seem to find the relevant document on Intel's site.  At least, 
this:

http://www.intel.com/content/www/us/en/processors/core/2nd-gen-core-family-
mobile-vol-2-datasheet.html

Does not seem to mention CPU0BUS0 anywhere that I can see.  Are these special 
MSRs or are they a config register in another PCI device?

> -----Original Message-----
> From: John Baldwin [mailto:jhb at freebsd.org] 
> Sent: Monday, November 14, 2011 3:07 PM
> To: freebsd-acpi at freebsd.org
> Cc: John Veit; Don Croft
> Subject: Re: Sandy Bridge Support for FBSD 8.1
> 
> On Monday, November 14, 2011 9:50:14 am John Veit wrote:
> > Motherboard: Dell R720 with 2 SandyBridge X6 CPU's I do not see some 
> > devices on the second CPU slot (e.g. the Integrated Memory
> Controller devices @ bus(127):slot(15):fn(0)). I do see the IMC devices on 
the first CPU Slot (bus(63):slot(15):fn(0)), however.
> > 
> > Please advise.
> > Thanks, John Veit
> > jveit at dell.com
> 
> Eh.  How are you seeing those devices in the first place?  My understanding 
is that these devices showed up on busses starting with bus 255 on down.  This 
is managed by the qpi driver in sys/x86/pci/qpi.c.  Hmm, it doesn't see any 
devices on my SB desktop machine here.  Ah.  It does a CPU ID check that needs 
to be updated.  However, are the buses defined to be 127 and 63 rather than
> 255 and 254 as they were on Nehalem/Westmere?  Is there formal documentation 
you can point me at (from Intel perhaps?) that explains the official method 
for discovering these PCI buses?
> 
> --
> John Baldwin
> 

-- 
John Baldwin