svn commit: r283176 - in vendor/llvm/dist: . autoconf cmake docs include/llvm/Config include/llvm/Target lib/Analysis lib/CodeGen lib/CodeGen/SelectionDAG lib/ExecutionEngine/RuntimeDyld lib/IR lib...
Dimitry Andric
dim at FreeBSD.org
Thu May 21 06:57:15 UTC 2015
Author: dim
Date: Thu May 21 06:57:07 2015
New Revision: 283176
URL: https://svnweb.freebsd.org/changeset/base/283176
Log:
Vendor import of llvm RELEASE_361/final tag r237755 (effectively, 3.6.1 release):
https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_361/final@237755
Added:
vendor/llvm/dist/test/Analysis/ScalarEvolution/pr22856.ll
vendor/llvm/dist/test/CodeGen/AArch64/implicit-sret.ll
vendor/llvm/dist/test/CodeGen/AArch64/machine-copy-prop.ll
vendor/llvm/dist/test/CodeGen/AArch64/tailcall-explicit-sret.ll
vendor/llvm/dist/test/CodeGen/AArch64/tailcall-implicit-sret.ll
vendor/llvm/dist/test/CodeGen/Mips/adjust-callstack-sp.ll
vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
vendor/llvm/dist/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
vendor/llvm/dist/test/CodeGen/Mips/check-adde-redundant-moves.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/add.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/and.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/ashr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/lshr.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/or.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/sdiv.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/shl.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/srem.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/sub.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/udiv.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/urem.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/xor.ll
vendor/llvm/dist/test/CodeGen/Mips/mips64signextendsesf.ll
vendor/llvm/dist/test/CodeGen/Mips/mips64sinttofpsf.ll
vendor/llvm/dist/test/CodeGen/Mips/no-odd-spreg-msa.ll
vendor/llvm/dist/test/CodeGen/R600/extload-private.ll
vendor/llvm/dist/test/CodeGen/R600/fdiv.f64.ll
vendor/llvm/dist/test/CodeGen/R600/fmax3.f64.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.flbit.i32.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.fs.interp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.sendmsg-m0.ll
vendor/llvm/dist/test/CodeGen/R600/si-annotate-cf.ll
vendor/llvm/dist/test/CodeGen/X86/and-load-fold.ll
vendor/llvm/dist/test/CodeGen/X86/dag-optnone.ll
vendor/llvm/dist/test/CodeGen/X86/getelementptr.ll
vendor/llvm/dist/test/CodeGen/X86/lower-vec-shuffle-bug.ll
vendor/llvm/dist/test/CodeGen/X86/pr22774.ll
vendor/llvm/dist/test/CodeGen/X86/scheduler-backtracking.ll
vendor/llvm/dist/test/CodeGen/X86/setcc-combine.ll
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r6/
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64/
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64/valid-mips64.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2/
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r6/
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (contents, props changed)
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt (contents, props changed)
vendor/llvm/dist/test/Transforms/ConstProp/shift.ll
vendor/llvm/dist/test/tools/llvm-cov/Inputs/test_exit_block_arcs.gcda (contents, props changed)
vendor/llvm/dist/test/tools/llvm-cov/Inputs/test_exit_block_arcs.gcno (contents, props changed)
Deleted:
vendor/llvm/dist/test/CodeGen/R600/fdiv64.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll
vendor/llvm/dist/test/CodeGen/X86/fastmath-optnone.ll
Modified:
vendor/llvm/dist/CMakeLists.txt
vendor/llvm/dist/autoconf/configure.ac
vendor/llvm/dist/cmake/config-ix.cmake
vendor/llvm/dist/configure
vendor/llvm/dist/docs/ReleaseNotes.rst
vendor/llvm/dist/include/llvm/Config/config.h.cmake
vendor/llvm/dist/include/llvm/Config/config.h.in
vendor/llvm/dist/include/llvm/Target/TargetCallingConv.h
vendor/llvm/dist/include/llvm/Target/TargetLowering.h
vendor/llvm/dist/lib/Analysis/ScalarEvolutionExpander.cpp
vendor/llvm/dist/lib/CodeGen/MachineCopyPropagation.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
vendor/llvm/dist/lib/IR/ConstantFold.cpp
vendor/llvm/dist/lib/IR/GCOV.cpp
vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp
vendor/llvm/dist/lib/Support/Unix/Memory.inc
vendor/llvm/dist/lib/Support/Windows/explicit_symbols.inc
vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp
vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.h
vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td
vendor/llvm/dist/lib/Target/AArch64/AArch64MCInstLower.cpp
vendor/llvm/dist/lib/Target/AArch64/Utils/AArch64BaseInfo.h
vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp
vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
vendor/llvm/dist/lib/Target/Mips/Mips.td
vendor/llvm/dist/lib/Target/Mips/Mips16InstrInfo.cpp
vendor/llvm/dist/lib/Target/Mips/Mips32r6InstrInfo.td
vendor/llvm/dist/lib/Target/Mips/Mips64InstrInfo.td
vendor/llvm/dist/lib/Target/Mips/MipsCCState.cpp
vendor/llvm/dist/lib/Target/Mips/MipsCallingConv.td
vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.cpp
vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h
vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td
vendor/llvm/dist/lib/Target/Mips/MipsRegisterInfo.td
vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
vendor/llvm/dist/lib/Target/Mips/MipsSEISelLowering.cpp
vendor/llvm/dist/lib/Target/Mips/MipsSEInstrInfo.cpp
vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPU.td
vendor/llvm/dist/lib/Target/R600/AMDGPUAlwaysInlinePass.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPUAsmPrinter.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPUISelLowering.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPUInstrInfo.h
vendor/llvm/dist/lib/Target/R600/AMDGPUInstrInfo.td
vendor/llvm/dist/lib/Target/R600/AMDGPUInstructions.td
vendor/llvm/dist/lib/Target/R600/AMDGPUIntrinsics.td
vendor/llvm/dist/lib/Target/R600/AMDGPUSubtarget.cpp
vendor/llvm/dist/lib/Target/R600/AMDGPUSubtarget.h
vendor/llvm/dist/lib/Target/R600/CaymanInstructions.td
vendor/llvm/dist/lib/Target/R600/EvergreenInstructions.td
vendor/llvm/dist/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
vendor/llvm/dist/lib/Target/R600/Processors.td
vendor/llvm/dist/lib/Target/R600/R600ISelLowering.cpp
vendor/llvm/dist/lib/Target/R600/R600Instructions.td
vendor/llvm/dist/lib/Target/R600/SIAnnotateControlFlow.cpp
vendor/llvm/dist/lib/Target/R600/SIDefines.h
vendor/llvm/dist/lib/Target/R600/SIFoldOperands.cpp
vendor/llvm/dist/lib/Target/R600/SIISelLowering.cpp
vendor/llvm/dist/lib/Target/R600/SIInsertWaits.cpp
vendor/llvm/dist/lib/Target/R600/SIInstrFormats.td
vendor/llvm/dist/lib/Target/R600/SIInstrInfo.cpp
vendor/llvm/dist/lib/Target/R600/SIInstrInfo.h
vendor/llvm/dist/lib/Target/R600/SIInstrInfo.td
vendor/llvm/dist/lib/Target/R600/SIInstructions.td
vendor/llvm/dist/lib/Target/R600/SILowerControlFlow.cpp
vendor/llvm/dist/lib/Target/R600/SIRegisterInfo.cpp
vendor/llvm/dist/lib/Target/R600/SIRegisterInfo.h
vendor/llvm/dist/lib/Target/R600/SIRegisterInfo.td
vendor/llvm/dist/lib/Target/R600/VIInstrFormats.td
vendor/llvm/dist/lib/Target/R600/VIInstructions.td
vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86FrameLowering.h
vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86InstrControl.td
vendor/llvm/dist/lib/Target/X86/X86IntrinsicsInfo.h
vendor/llvm/dist/lib/Transforms/Instrumentation/GCOVProfiling.cpp
vendor/llvm/dist/lib/Transforms/Scalar/GVN.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LoopRotation.cpp
vendor/llvm/dist/lib/Transforms/Utils/SimplifyIndVar.cpp
vendor/llvm/dist/test/CodeGen/AArch64/arm64-tls-dynamics.ll
vendor/llvm/dist/test/CodeGen/AArch64/arm64-tls-execs.ll
vendor/llvm/dist/test/CodeGen/Mips/fcmp.ll
vendor/llvm/dist/test/CodeGen/Mips/fmadd1.ll
vendor/llvm/dist/test/CodeGen/Mips/llvm-ir/mul.ll
vendor/llvm/dist/test/CodeGen/Mips/mips64-f128.ll
vendor/llvm/dist/test/CodeGen/R600/128bit-kernel-args.ll
vendor/llvm/dist/test/CodeGen/R600/32-bit-local-address-space.ll
vendor/llvm/dist/test/CodeGen/R600/64bit-kernel-args.ll
vendor/llvm/dist/test/CodeGen/R600/add-debug.ll
vendor/llvm/dist/test/CodeGen/R600/add.ll
vendor/llvm/dist/test/CodeGen/R600/address-space.ll
vendor/llvm/dist/test/CodeGen/R600/and.ll
vendor/llvm/dist/test/CodeGen/R600/anyext.ll
vendor/llvm/dist/test/CodeGen/R600/atomic_load_add.ll
vendor/llvm/dist/test/CodeGen/R600/atomic_load_sub.ll
vendor/llvm/dist/test/CodeGen/R600/basic-branch.ll
vendor/llvm/dist/test/CodeGen/R600/basic-loop.ll
vendor/llvm/dist/test/CodeGen/R600/bfi_int.ll
vendor/llvm/dist/test/CodeGen/R600/bitcast.ll
vendor/llvm/dist/test/CodeGen/R600/bswap.ll
vendor/llvm/dist/test/CodeGen/R600/build_vector.ll
vendor/llvm/dist/test/CodeGen/R600/call.ll
vendor/llvm/dist/test/CodeGen/R600/call_fs.ll
vendor/llvm/dist/test/CodeGen/R600/cf_end.ll
vendor/llvm/dist/test/CodeGen/R600/concat_vectors.ll
vendor/llvm/dist/test/CodeGen/R600/copy-illegal-type.ll
vendor/llvm/dist/test/CodeGen/R600/copy-to-reg.ll
vendor/llvm/dist/test/CodeGen/R600/ctlz_zero_undef.ll
vendor/llvm/dist/test/CodeGen/R600/cttz-ctlz.ll
vendor/llvm/dist/test/CodeGen/R600/cttz_zero_undef.ll
vendor/llvm/dist/test/CodeGen/R600/cvt_f32_ubyte.ll
vendor/llvm/dist/test/CodeGen/R600/default-fp-mode.ll
vendor/llvm/dist/test/CodeGen/R600/ds_read2_offset_order.ll
vendor/llvm/dist/test/CodeGen/R600/elf.ll
vendor/llvm/dist/test/CodeGen/R600/elf.r600.ll
vendor/llvm/dist/test/CodeGen/R600/empty-function.ll
vendor/llvm/dist/test/CodeGen/R600/extload.ll
vendor/llvm/dist/test/CodeGen/R600/extract_vector_elt_i16.ll
vendor/llvm/dist/test/CodeGen/R600/fadd.ll
vendor/llvm/dist/test/CodeGen/R600/fadd64.ll
vendor/llvm/dist/test/CodeGen/R600/fceil.ll
vendor/llvm/dist/test/CodeGen/R600/fcmp64.ll
vendor/llvm/dist/test/CodeGen/R600/fconst64.ll
vendor/llvm/dist/test/CodeGen/R600/fdiv.ll
vendor/llvm/dist/test/CodeGen/R600/ffloor.ll
vendor/llvm/dist/test/CodeGen/R600/flat-address-space.ll
vendor/llvm/dist/test/CodeGen/R600/fma.f64.ll
vendor/llvm/dist/test/CodeGen/R600/fmax3.ll
vendor/llvm/dist/test/CodeGen/R600/fmaxnum.f64.ll
vendor/llvm/dist/test/CodeGen/R600/fmaxnum.ll
vendor/llvm/dist/test/CodeGen/R600/fmin3.ll
vendor/llvm/dist/test/CodeGen/R600/fminnum.f64.ll
vendor/llvm/dist/test/CodeGen/R600/fminnum.ll
vendor/llvm/dist/test/CodeGen/R600/fmul.ll
vendor/llvm/dist/test/CodeGen/R600/fmul64.ll
vendor/llvm/dist/test/CodeGen/R600/fnearbyint.ll
vendor/llvm/dist/test/CodeGen/R600/fneg-fabs.f64.ll
vendor/llvm/dist/test/CodeGen/R600/fneg-fabs.ll
vendor/llvm/dist/test/CodeGen/R600/fp-classify.ll
vendor/llvm/dist/test/CodeGen/R600/fp16_to_fp.ll
vendor/llvm/dist/test/CodeGen/R600/fp32_to_fp16.ll
vendor/llvm/dist/test/CodeGen/R600/fp_to_sint.ll
vendor/llvm/dist/test/CodeGen/R600/fp_to_uint.ll
vendor/llvm/dist/test/CodeGen/R600/fpext.ll
vendor/llvm/dist/test/CodeGen/R600/fptrunc.ll
vendor/llvm/dist/test/CodeGen/R600/frem.ll
vendor/llvm/dist/test/CodeGen/R600/fsqrt.ll
vendor/llvm/dist/test/CodeGen/R600/fsub.ll
vendor/llvm/dist/test/CodeGen/R600/fsub64.ll
vendor/llvm/dist/test/CodeGen/R600/ftrunc.ll
vendor/llvm/dist/test/CodeGen/R600/global-directive.ll
vendor/llvm/dist/test/CodeGen/R600/global-extload-i1.ll
vendor/llvm/dist/test/CodeGen/R600/global-extload-i16.ll
vendor/llvm/dist/test/CodeGen/R600/global-extload-i32.ll
vendor/llvm/dist/test/CodeGen/R600/global-extload-i8.ll
vendor/llvm/dist/test/CodeGen/R600/global-zero-initializer.ll
vendor/llvm/dist/test/CodeGen/R600/half.ll
vendor/llvm/dist/test/CodeGen/R600/i1-copy-implicit-def.ll
vendor/llvm/dist/test/CodeGen/R600/i1-copy-phi.ll
vendor/llvm/dist/test/CodeGen/R600/icmp64.ll
vendor/llvm/dist/test/CodeGen/R600/indirect-addressing-si.ll
vendor/llvm/dist/test/CodeGen/R600/indirect-private-64.ll
vendor/llvm/dist/test/CodeGen/R600/infinite-loop.ll
vendor/llvm/dist/test/CodeGen/R600/inline-asm.ll
vendor/llvm/dist/test/CodeGen/R600/inline-calls.ll
vendor/llvm/dist/test/CodeGen/R600/input-mods.ll
vendor/llvm/dist/test/CodeGen/R600/insert_subreg.ll
vendor/llvm/dist/test/CodeGen/R600/insert_vector_elt.ll
vendor/llvm/dist/test/CodeGen/R600/kernel-args.ll
vendor/llvm/dist/test/CodeGen/R600/large-alloca.ll
vendor/llvm/dist/test/CodeGen/R600/large-constant-initializer.ll
vendor/llvm/dist/test/CodeGen/R600/lds-initializer.ll
vendor/llvm/dist/test/CodeGen/R600/lds-zero-initializer.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.abs.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.bfe.u32.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.bfi.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.bfm.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.brev.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.clamp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.cvt_f32_ubyte.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.div_fmas.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.div_scale.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.fract.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.imad24.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.imax.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.imin.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.imul24.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.kill.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.ldexp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.rcp.f64.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.rcp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.rsq.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.trig_preop.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.umax.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.umin.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.AMDGPU.umul24.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.gather4.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.getlod.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.image.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.image.sample.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.image.sample.o.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.imageload.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.load.dword.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.resinfo.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.sample-masked.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.sample.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.sampled.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.sendmsg.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.SI.tbuffer.store.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.amdgpu.kilp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.amdgpu.lrp.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.cos.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.exp2.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.log2.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.memcpy.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.rint.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.sin.ll
vendor/llvm/dist/test/CodeGen/R600/llvm.sqrt.ll
vendor/llvm/dist/test/CodeGen/R600/load-i1.ll
vendor/llvm/dist/test/CodeGen/R600/load.ll
vendor/llvm/dist/test/CodeGen/R600/load.vec.ll
vendor/llvm/dist/test/CodeGen/R600/load64.ll
vendor/llvm/dist/test/CodeGen/R600/local-memory-two-objects.ll
vendor/llvm/dist/test/CodeGen/R600/loop-idiom.ll
vendor/llvm/dist/test/CodeGen/R600/lshl.ll
vendor/llvm/dist/test/CodeGen/R600/lshr.ll
vendor/llvm/dist/test/CodeGen/R600/m0-spill.ll
vendor/llvm/dist/test/CodeGen/R600/mad_int24.ll
vendor/llvm/dist/test/CodeGen/R600/mad_uint24.ll
vendor/llvm/dist/test/CodeGen/R600/mul.ll
vendor/llvm/dist/test/CodeGen/R600/mul_int24.ll
vendor/llvm/dist/test/CodeGen/R600/mul_uint24.ll
vendor/llvm/dist/test/CodeGen/R600/mulhu.ll
vendor/llvm/dist/test/CodeGen/R600/no-initializer-constant-addrspace.ll
vendor/llvm/dist/test/CodeGen/R600/or.ll
vendor/llvm/dist/test/CodeGen/R600/private-memory-atomics.ll
vendor/llvm/dist/test/CodeGen/R600/private-memory-broken.ll
vendor/llvm/dist/test/CodeGen/R600/r600-encoding.ll
vendor/llvm/dist/test/CodeGen/R600/reorder-stores.ll
vendor/llvm/dist/test/CodeGen/R600/rotl.i64.ll
vendor/llvm/dist/test/CodeGen/R600/rotl.ll
vendor/llvm/dist/test/CodeGen/R600/rotr.i64.ll
vendor/llvm/dist/test/CodeGen/R600/rotr.ll
vendor/llvm/dist/test/CodeGen/R600/s_movk_i32.ll
vendor/llvm/dist/test/CodeGen/R600/saddo.ll
vendor/llvm/dist/test/CodeGen/R600/scalar_to_vector.ll
vendor/llvm/dist/test/CodeGen/R600/schedule-kernel-arg-loads.ll
vendor/llvm/dist/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
vendor/llvm/dist/test/CodeGen/R600/sdiv.ll
vendor/llvm/dist/test/CodeGen/R600/sdivrem24.ll
vendor/llvm/dist/test/CodeGen/R600/select-i1.ll
vendor/llvm/dist/test/CodeGen/R600/select-vectors.ll
vendor/llvm/dist/test/CodeGen/R600/select64.ll
vendor/llvm/dist/test/CodeGen/R600/selectcc-opt.ll
vendor/llvm/dist/test/CodeGen/R600/selectcc.ll
vendor/llvm/dist/test/CodeGen/R600/setcc64.ll
vendor/llvm/dist/test/CodeGen/R600/seto.ll
vendor/llvm/dist/test/CodeGen/R600/setuo.ll
vendor/llvm/dist/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
vendor/llvm/dist/test/CodeGen/R600/sgpr-copy.ll
vendor/llvm/dist/test/CodeGen/R600/shl.ll
vendor/llvm/dist/test/CodeGen/R600/shl_add_ptr.ll
vendor/llvm/dist/test/CodeGen/R600/si-annotate-cf-assertion.ll
vendor/llvm/dist/test/CodeGen/R600/si-lod-bias.ll
vendor/llvm/dist/test/CodeGen/R600/si-sgpr-spill.ll
vendor/llvm/dist/test/CodeGen/R600/si-vector-hang.ll
vendor/llvm/dist/test/CodeGen/R600/sign_extend.ll
vendor/llvm/dist/test/CodeGen/R600/simplify-demanded-bits-build-pair.ll
vendor/llvm/dist/test/CodeGen/R600/sint_to_fp.ll
vendor/llvm/dist/test/CodeGen/R600/sra.ll
vendor/llvm/dist/test/CodeGen/R600/srem.ll
vendor/llvm/dist/test/CodeGen/R600/ssubo.ll
vendor/llvm/dist/test/CodeGen/R600/store-v3i32.ll
vendor/llvm/dist/test/CodeGen/R600/store-v3i64.ll
vendor/llvm/dist/test/CodeGen/R600/store-vector-ptrs.ll
vendor/llvm/dist/test/CodeGen/R600/store.ll
vendor/llvm/dist/test/CodeGen/R600/store.r600.ll
vendor/llvm/dist/test/CodeGen/R600/subreg-coalescer-crash.ll
vendor/llvm/dist/test/CodeGen/R600/swizzle-export.ll
vendor/llvm/dist/test/CodeGen/R600/trunc-cmp-constant.ll
vendor/llvm/dist/test/CodeGen/R600/trunc-store-i1.ll
vendor/llvm/dist/test/CodeGen/R600/trunc.ll
vendor/llvm/dist/test/CodeGen/R600/uaddo.ll
vendor/llvm/dist/test/CodeGen/R600/udiv.ll
vendor/llvm/dist/test/CodeGen/R600/udivrem.ll
vendor/llvm/dist/test/CodeGen/R600/udivrem24.ll
vendor/llvm/dist/test/CodeGen/R600/udivrem64.ll
vendor/llvm/dist/test/CodeGen/R600/uint_to_fp.ll
vendor/llvm/dist/test/CodeGen/R600/unaligned-load-store.ll
vendor/llvm/dist/test/CodeGen/R600/unhandled-loop-condition-assertion.ll
vendor/llvm/dist/test/CodeGen/R600/urecip.ll
vendor/llvm/dist/test/CodeGen/R600/urem.ll
vendor/llvm/dist/test/CodeGen/R600/usubo.ll
vendor/llvm/dist/test/CodeGen/R600/v_cndmask.ll
vendor/llvm/dist/test/CodeGen/R600/vector-alloca.ll
vendor/llvm/dist/test/CodeGen/R600/vertex-fetch-encoding.ll
vendor/llvm/dist/test/CodeGen/R600/vop-shrink.ll
vendor/llvm/dist/test/CodeGen/R600/vselect.ll
vendor/llvm/dist/test/CodeGen/R600/wait.ll
vendor/llvm/dist/test/CodeGen/R600/xor.ll
vendor/llvm/dist/test/CodeGen/R600/zero_extend.ll
vendor/llvm/dist/test/CodeGen/X86/avx-vperm2x128.ll
vendor/llvm/dist/test/CodeGen/X86/avx2-intrinsics-x86.ll
vendor/llvm/dist/test/CodeGen/X86/inalloca-stdcall.ll
vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-512-v8.ll
vendor/llvm/dist/test/CodeGen/X86/win64_alloca_dynalloca.ll
vendor/llvm/dist/test/CodeGen/X86/win_chkstk.ll
vendor/llvm/dist/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s
vendor/llvm/dist/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips1/valid-xfail.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32/valid-xfail-mips32.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
vendor/llvm/dist/test/MC/ELF/uleb.s
vendor/llvm/dist/test/MC/Mips/mips-abi-bad.s
vendor/llvm/dist/test/MC/Mips/mips4/invalid-mips64r2.s
vendor/llvm/dist/test/MC/Mips/mips4/valid-xfail.s
vendor/llvm/dist/test/MC/Mips/mips4/valid.s
vendor/llvm/dist/test/MC/Mips/mips5/invalid-mips64r2.s
vendor/llvm/dist/test/MC/Mips/mips5/valid-xfail.s
vendor/llvm/dist/test/MC/Mips/mips5/valid.s
vendor/llvm/dist/test/MC/Mips/mips64/invalid-mips64r2.s
vendor/llvm/dist/test/MC/Mips/mips64/valid-xfail.s
vendor/llvm/dist/test/MC/Mips/mips64/valid.s
vendor/llvm/dist/test/MC/Mips/mips64r2/abi-bad.s
vendor/llvm/dist/test/MC/Mips/mips64r2/valid-xfail.s
vendor/llvm/dist/test/Transforms/GCOVProfiling/return-block.ll
vendor/llvm/dist/test/Transforms/GVN/edge.ll
vendor/llvm/dist/test/Transforms/LoopRotate/crash.ll
vendor/llvm/dist/test/tools/llvm-cov/llvm-cov.test
vendor/llvm/dist/utils/release/tag.sh
Modified: vendor/llvm/dist/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/CMakeLists.txt Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/CMakeLists.txt Thu May 21 06:57:07 2015 (r283176)
@@ -48,7 +48,7 @@ set(CMAKE_MODULE_PATH
set(LLVM_VERSION_MAJOR 3)
set(LLVM_VERSION_MINOR 6)
-set(LLVM_VERSION_PATCH 0)
+set(LLVM_VERSION_PATCH 1)
if (NOT PACKAGE_VERSION)
set(PACKAGE_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}")
Modified: vendor/llvm/dist/autoconf/configure.ac
==============================================================================
--- vendor/llvm/dist/autoconf/configure.ac Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/autoconf/configure.ac Thu May 21 06:57:07 2015 (r283176)
@@ -32,11 +32,11 @@ dnl===----------------------------------
dnl Initialize autoconf and define the package name, version number and
dnl address for reporting bugs.
-AC_INIT([LLVM],[3.6.0],[http://llvm.org/bugs/])
+AC_INIT([LLVM],[3.6.1],[http://llvm.org/bugs/])
LLVM_VERSION_MAJOR=3
LLVM_VERSION_MINOR=6
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
LLVM_VERSION_SUFFIX=
AC_DEFINE_UNQUOTED([LLVM_VERSION_MAJOR], $LLVM_VERSION_MAJOR, [Major version of the LLVM API])
@@ -1714,7 +1714,9 @@ if test "$llvm_cv_os_type" = "MingW" ; t
AC_CHECK_LIB(gcc,_alloca,AC_DEFINE([HAVE__ALLOCA],[1],[Have host's _alloca]))
AC_CHECK_LIB(gcc,__alloca,AC_DEFINE([HAVE___ALLOCA],[1],[Have host's __alloca]))
AC_CHECK_LIB(gcc,__chkstk,AC_DEFINE([HAVE___CHKSTK],[1],[Have host's __chkstk]))
+ AC_CHECK_LIB(gcc,__chkstk_ms,AC_DEFINE([HAVE___CHKSTK_MS],[1],[Have host's __chkstk_ms]))
AC_CHECK_LIB(gcc,___chkstk,AC_DEFINE([HAVE____CHKSTK],[1],[Have host's ___chkstk]))
+ AC_CHECK_LIB(gcc,___chkstk_ms,AC_DEFINE([HAVE____CHKSTK_MS],[1],[Have host's ___chkstk_ms]))
AC_CHECK_LIB(gcc,__ashldi3,AC_DEFINE([HAVE___ASHLDI3],[1],[Have host's __ashldi3]))
AC_CHECK_LIB(gcc,__ashrdi3,AC_DEFINE([HAVE___ASHRDI3],[1],[Have host's __ashrdi3]))
Modified: vendor/llvm/dist/cmake/config-ix.cmake
==============================================================================
--- vendor/llvm/dist/cmake/config-ix.cmake Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/cmake/config-ix.cmake Thu May 21 06:57:07 2015 (r283176)
@@ -198,7 +198,9 @@ if( PURE_WINDOWS )
check_function_exists(_alloca HAVE__ALLOCA)
check_function_exists(__alloca HAVE___ALLOCA)
check_function_exists(__chkstk HAVE___CHKSTK)
+ check_function_exists(__chkstk_ms HAVE___CHKSTK_MS)
check_function_exists(___chkstk HAVE____CHKSTK)
+ check_function_exists(___chkstk_ms HAVE____CHKSTK_MS)
check_function_exists(__ashldi3 HAVE___ASHLDI3)
check_function_exists(__ashrdi3 HAVE___ASHRDI3)
Modified: vendor/llvm/dist/configure
==============================================================================
--- vendor/llvm/dist/configure Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/configure Thu May 21 06:57:07 2015 (r283176)
@@ -1,6 +1,6 @@
#! /bin/sh
# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.60 for LLVM 3.6.0.
+# Generated by GNU Autoconf 2.60 for LLVM 3.6.1.
#
# Report bugs to <http://llvm.org/bugs/>.
#
@@ -561,8 +561,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
# Identity of this package.
PACKAGE_NAME='LLVM'
PACKAGE_TARNAME='llvm'
-PACKAGE_VERSION='3.6.0'
-PACKAGE_STRING='LLVM 3.6.0'
+PACKAGE_VERSION='3.6.1'
+PACKAGE_STRING='LLVM 3.6.1'
PACKAGE_BUGREPORT='http://llvm.org/bugs/'
ac_unique_file="lib/IR/Module.cpp"
@@ -1314,7 +1314,7 @@ if test "$ac_init_help" = "long"; then
# Omit some internal or obsolete options to make the list less imposing.
# This message is too long to be a string in the A/UX 3.1 sh.
cat <<_ACEOF
-\`configure' configures LLVM 3.6.0 to adapt to many kinds of systems.
+\`configure' configures LLVM 3.6.1 to adapt to many kinds of systems.
Usage: $0 [OPTION]... [VAR=VALUE]...
@@ -1380,7 +1380,7 @@ fi
if test -n "$ac_init_help"; then
case $ac_init_help in
- short | recursive ) echo "Configuration of LLVM 3.6.0:";;
+ short | recursive ) echo "Configuration of LLVM 3.6.1:";;
esac
cat <<\_ACEOF
@@ -1550,7 +1550,7 @@ fi
test -n "$ac_init_help" && exit $ac_status
if $ac_init_version; then
cat <<\_ACEOF
-LLVM configure 3.6.0
+LLVM configure 3.6.1
generated by GNU Autoconf 2.60
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
@@ -1566,7 +1566,7 @@ cat >config.log <<_ACEOF
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
-It was created by LLVM $as_me 3.6.0, which was
+It was created by LLVM $as_me 3.6.1, which was
generated by GNU Autoconf 2.60. Invocation command line was
$ $0 $@
@@ -1922,7 +1922,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
LLVM_VERSION_MAJOR=3
LLVM_VERSION_MINOR=6
-LLVM_VERSION_PATCH=0
+LLVM_VERSION_PATCH=1
LLVM_VERSION_SUFFIX=
@@ -15438,6 +15438,91 @@ _ACEOF
fi
+ { echo "$as_me:$LINENO: checking for __chkstk_ms in -lgcc" >&5
+echo $ECHO_N "checking for __chkstk_ms in -lgcc... $ECHO_C" >&6; }
+if test "${ac_cv_lib_gcc___chkstk_ms+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lgcc $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char __chkstk_ms ();
+int
+main ()
+{
+return __chkstk_ms ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_link") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_gcc___chkstk_ms=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_cv_lib_gcc___chkstk_ms=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ echo "$as_me:$LINENO: result: $ac_cv_lib_gcc___chkstk_ms" >&5
+echo "${ECHO_T}$ac_cv_lib_gcc___chkstk_ms" >&6; }
+if test $ac_cv_lib_gcc___chkstk_ms = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE___CHKSTK_MS 1
+_ACEOF
+
+fi
+
{ echo "$as_me:$LINENO: checking for ___chkstk in -lgcc" >&5
echo $ECHO_N "checking for ___chkstk in -lgcc... $ECHO_C" >&6; }
if test "${ac_cv_lib_gcc____chkstk+set}" = set; then
@@ -15523,6 +15608,91 @@ _ACEOF
fi
+ { echo "$as_me:$LINENO: checking for ___chkstk_ms in -lgcc" >&5
+echo $ECHO_N "checking for ___chkstk_ms in -lgcc... $ECHO_C" >&6; }
+if test "${ac_cv_lib_gcc____chkstk_ms+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lgcc $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any GCC internal prototype to avoid an error.
+ Use char because int might match the return type of a GCC
+ builtin and then its argument prototype would still apply. */
+#ifdef __cplusplus
+extern "C"
+#endif
+char ___chkstk_ms ();
+int
+main ()
+{
+return ___chkstk_ms ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (ac_try="$ac_link"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_link") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_gcc____chkstk_ms=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_cv_lib_gcc____chkstk_ms=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ echo "$as_me:$LINENO: result: $ac_cv_lib_gcc____chkstk_ms" >&5
+echo "${ECHO_T}$ac_cv_lib_gcc____chkstk_ms" >&6; }
+if test $ac_cv_lib_gcc____chkstk_ms = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE____CHKSTK_MS 1
+_ACEOF
+
+fi
+
{ echo "$as_me:$LINENO: checking for __ashldi3 in -lgcc" >&5
echo $ECHO_N "checking for __ashldi3 in -lgcc... $ECHO_C" >&6; }
@@ -18901,7 +19071,7 @@ exec 6>&1
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
-This file was extended by LLVM $as_me 3.6.0, which was
+This file was extended by LLVM $as_me 3.6.1, which was
generated by GNU Autoconf 2.60. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
@@ -18954,7 +19124,7 @@ Report bugs to <bug-autoconf at gnu.org>."
_ACEOF
cat >>$CONFIG_STATUS <<_ACEOF
ac_cs_version="\\
-LLVM config.status 3.6.0
+LLVM config.status 3.6.1
configured by $0, generated by GNU Autoconf 2.60,
with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
Modified: vendor/llvm/dist/docs/ReleaseNotes.rst
==============================================================================
--- vendor/llvm/dist/docs/ReleaseNotes.rst Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/docs/ReleaseNotes.rst Thu May 21 06:57:07 2015 (r283176)
@@ -25,6 +25,31 @@ them.
Non-comprehensive list of changes in this release
=================================================
+Changes to the MIPS Target
+--------------------------
+
+* Added support for 128-bit integers on 64-bit targets.
+
+* Fixed some remaining N32/N64 calling convention bugs when using small
+ structures on big-endian targets.
+
+* Fixed missing sign-extensions that are required by the N32/N64 calling
+ convention when generating calls to library functions with 32-bit parameters.
+
+* ``-mno-odd-spreg`` is now honoured for vector insertion/extraction operations
+ when using ``-mmsa``.
+
+* Corrected the representation of member function pointers. This makes them
+ usable on microMIPS targets.
+
+* Fixed multiple segfaults and assertions in the disassembler when
+ disassembling instructions that have memory operands.
+
+* Fixed multiple cases of suboptimal code generation involving ``$zero``.
+
+Non-comprehensive list of changes in 3.6.0
+==========================================
+
.. NOTE
For small 1-3 sentence descriptions, just add an entry at the end of
this list. If your description won't fit comfortably in one bullet
Modified: vendor/llvm/dist/include/llvm/Config/config.h.cmake
==============================================================================
--- vendor/llvm/dist/include/llvm/Config/config.h.cmake Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/include/llvm/Config/config.h.cmake Thu May 21 06:57:07 2015 (r283176)
@@ -423,6 +423,9 @@
/* Have host's __chkstk */
#cmakedefine HAVE___CHKSTK ${HAVE___CHKSTK}
+/* Have host's __chkstk_ms */
+#cmakedefine HAVE___CHKSTK_MS ${HAVE___CHKSTK_MS}
+
/* Have host's __cmpdi2 */
#cmakedefine HAVE___CMPDI2 ${HAVE___CMPDI2}
@@ -459,6 +462,9 @@
/* Have host's ___chkstk */
#cmakedefine HAVE____CHKSTK ${HAVE____CHKSTK}
+/* Have host's ___chkstk_ms */
+#cmakedefine HAVE____CHKSTK_MS ${HAVE____CHKSTK_MS}
+
/* Define if we link Polly to the tools */
#cmakedefine LINK_POLLY_INTO_TOOLS
Modified: vendor/llvm/dist/include/llvm/Config/config.h.in
==============================================================================
--- vendor/llvm/dist/include/llvm/Config/config.h.in Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/include/llvm/Config/config.h.in Thu May 21 06:57:07 2015 (r283176)
@@ -420,6 +420,9 @@
/* Have host's __chkstk */
#undef HAVE___CHKSTK
+/* Have host's __chkstk_ms */
+#undef HAVE___CHKSTK_MS
+
/* Have host's __cmpdi2 */
#undef HAVE___CMPDI2
@@ -456,6 +459,9 @@
/* Have host's ___chkstk */
#undef HAVE____CHKSTK
+/* Have host's ___chkstk_ms */
+#undef HAVE____CHKSTK_MS
+
/* Linker version detected at compile time. */
#undef HOST_LINK_VERSION
Modified: vendor/llvm/dist/include/llvm/Target/TargetCallingConv.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Target/TargetCallingConv.h Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/include/llvm/Target/TargetCallingConv.h Thu May 21 06:57:07 2015 (r283176)
@@ -134,6 +134,8 @@ namespace ISD {
/// Index original Function's argument.
unsigned OrigArgIndex;
+ /// Sentinel value for implicit machine-level input arguments.
+ static const unsigned NoArgIndex = UINT_MAX;
/// Offset in bytes of current input value relative to the beginning of
/// original argument. E.g. if argument was splitted into four 32 bit
@@ -147,6 +149,15 @@ namespace ISD {
VT = vt.getSimpleVT();
ArgVT = argvt;
}
+
+ bool isOrigArg() const {
+ return OrigArgIndex != NoArgIndex;
+ }
+
+ unsigned getOrigArgIndex() const {
+ assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument");
+ return OrigArgIndex;
+ }
};
/// OutputArg - This struct carries flags and a value for a
Modified: vendor/llvm/dist/include/llvm/Target/TargetLowering.h
==============================================================================
--- vendor/llvm/dist/include/llvm/Target/TargetLowering.h Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/include/llvm/Target/TargetLowering.h Thu May 21 06:57:07 2015 (r283176)
@@ -2806,6 +2806,11 @@ public:
virtual bool useLoadStackGuardNode() const {
return false;
}
+
+ /// Returns true if arguments should be sign-extended in lib calls.
+ virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
+ return IsSigned;
+ }
};
/// Given an LLVM IR type and return type attributes, compute the return value
Modified: vendor/llvm/dist/lib/Analysis/ScalarEvolutionExpander.cpp
==============================================================================
--- vendor/llvm/dist/lib/Analysis/ScalarEvolutionExpander.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Analysis/ScalarEvolutionExpander.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -1776,9 +1776,12 @@ unsigned SCEVExpander::replaceCongruentI
<< *IsomorphicInc << '\n');
Value *NewInc = OrigInc;
if (OrigInc->getType() != IsomorphicInc->getType()) {
- Instruction *IP = isa<PHINode>(OrigInc)
- ? (Instruction*)L->getHeader()->getFirstInsertionPt()
- : OrigInc->getNextNode();
+ Instruction *IP = nullptr;
+ if (PHINode *PN = dyn_cast<PHINode>(OrigInc))
+ IP = PN->getParent()->getFirstInsertionPt();
+ else
+ IP = OrigInc->getNextNode();
+
IRBuilder<> Builder(IP);
Builder.SetCurrentDebugLocation(IsomorphicInc->getDebugLoc());
NewInc = Builder.
Modified: vendor/llvm/dist/lib/CodeGen/MachineCopyPropagation.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/MachineCopyPropagation.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/MachineCopyPropagation.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -75,10 +75,9 @@ MachineCopyPropagation::SourceNoLongerAv
I != E; ++I) {
unsigned MappedDef = *I;
// Source of copy is no longer available for propagation.
- if (AvailCopyMap.erase(MappedDef)) {
- for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR)
- AvailCopyMap.erase(*SR);
- }
+ AvailCopyMap.erase(MappedDef);
+ for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR)
+ AvailCopyMap.erase(*SR);
}
}
}
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -1160,13 +1160,6 @@ void DAGCombiner::Run(CombineLevel AtLev
LegalOperations = Level >= AfterLegalizeVectorOps;
LegalTypes = Level >= AfterLegalizeTypes;
- // Early exit if this basic block is in an optnone function.
- AttributeSet FnAttrs =
- DAG.getMachineFunction().getFunction()->getAttributes();
- if (FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
- Attribute::OptimizeNone))
- return;
-
// Add all the dag nodes to the worklist.
for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
E = DAG.allnodes_end(); I != E; ++I)
@@ -2788,9 +2781,13 @@ SDValue DAGCombiner::visitAND(SDNode *N)
SplatBitSize = SplatBitSize * 2)
SplatValue |= SplatValue.shl(SplatBitSize);
- Constant = APInt::getAllOnesValue(BitWidth);
- for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
- Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
+ // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
+ // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
+ if (SplatBitSize % BitWidth == 0) {
+ Constant = APInt::getAllOnesValue(BitWidth);
+ for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
+ Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
+ }
}
}
@@ -11043,7 +11040,9 @@ SDValue DAGCombiner::visitBUILD_VECTOR(S
} else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
// If the input vector is too large, try to split it.
// We don't support having two input vectors that are too large.
- if (VecIn2.getNode())
+ // If the zero vector was used, we can not split the vector,
+ // since we'd need 3 inputs.
+ if (UsesZeroVector || VecIn2.getNode())
return SDValue();
if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
@@ -11055,7 +11054,6 @@ SDValue DAGCombiner::visitBUILD_VECTOR(S
DAG.getConstant(VT.getVectorNumElements(), TLI.getVectorIdxTy()));
VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
DAG.getConstant(0, TLI.getVectorIdxTy()));
- UsesZeroVector = false;
} else
return SDValue();
}
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -497,7 +497,7 @@ bool FastISel::selectGetElementPtr(const
OI != E; ++OI) {
const Value *Idx = *OI;
if (auto *StTy = dyn_cast<StructType>(Ty)) {
- unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
+ uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
if (Field) {
// N = N + Offset
TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
@@ -518,8 +518,8 @@ bool FastISel::selectGetElementPtr(const
if (CI->isZero())
continue;
// N = N + Offset
- TotalOffs +=
- DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue();
+ uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
+ TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
if (TotalOffs >= MaxOffs) {
N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
if (!N) // Unhandled operand. Halt "fast" selection and bail.
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -658,7 +658,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes
NVT, N->getOperand(0));
return TLI.makeLibCall(DAG, LC,
TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
- &Op, 1, false, dl).first;
+ &Op, 1, Signed, dl).first;
}
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -1423,9 +1423,10 @@ SUnit *ScheduleDAGRRList::PickNodeToSche
// If one or more successors has been unscheduled, then the current
// node is no longer available.
- if (!TrySU->isAvailable)
+ if (!TrySU->isAvailable || !TrySU->NodeQueueId)
CurSU = AvailableQueue->pop();
else {
+ // Available and in AvailableQueue
AvailableQueue->remove(TrySU);
CurSU = TrySU;
}
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -3399,30 +3399,21 @@ void SelectionDAGBuilder::visitGetElemen
Ty = StTy->getElementType(Field);
} else {
Ty = cast<SequentialType>(Ty)->getElementType();
+ MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
+ unsigned PtrSize = PtrTy.getSizeInBits();
+ APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
// If this is a constant subscript, handle it quickly.
- const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
- if (CI->isZero()) continue;
- uint64_t Offs =
- DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
- SDValue OffsVal;
- EVT PTy = TLI.getPointerTy(AS);
- unsigned PtrBits = PTy.getSizeInBits();
- if (PtrBits < 64)
- OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
- DAG.getConstant(Offs, MVT::i64));
- else
- OffsVal = DAG.getConstant(Offs, PTy);
-
- N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
- OffsVal);
+ if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
+ if (CI->isZero())
+ continue;
+ APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
+ SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
+ N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
continue;
}
// N = N + Idx * ElementSize;
- APInt ElementSize =
- APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
SDValue IdxN = getValue(Idx);
// If the index is smaller or larger than intptr_t, truncate or extend
@@ -5727,6 +5718,11 @@ void SelectionDAGBuilder::LowerCallTo(Im
// Skip the first return-type Attribute to get to params.
Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
Args.push_back(Entry);
+
+ // If we have an explicit sret argument that is an Instruction, (i.e., it
+ // might point to function-local memory), we can't meaningfully tail-call.
+ if (Entry.isSRet && isa<Instruction>(V))
+ isTailCall = false;
}
// Check if target-independent constraints permit a tail call here.
@@ -7353,6 +7349,10 @@ TargetLowering::LowerCallTo(TargetLoweri
Entry.Alignment = Align;
CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
+
+ // sret demotion isn't compatible with tail-calls, since the sret argument
+ // points into the callers stack frame.
+ CLI.IsTailCall = false;
} else {
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
EVT VT = RetTys[I];
@@ -7638,7 +7638,8 @@ void SelectionDAGISel::LowerArguments(co
ISD::ArgFlagsTy Flags;
Flags.setSRet();
MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
- ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
+ ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
+ ISD::InputArg::NoArgIndex, 0);
Ins.push_back(RetArg);
}
Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -96,18 +96,19 @@ TargetLowering::makeLibCall(SelectionDAG
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
- Entry.isSExt = isSigned;
- Entry.isZExt = !isSigned;
+ Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
+ Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
Args.push_back(Entry);
}
SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
TargetLowering::CallLoweringInfo CLI(DAG);
+ bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
.setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
.setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
- .setSExtResult(isSigned).setZExtResult(!isSigned);
+ .setSExtResult(signExtend).setZExtResult(!signExtend);
return LowerCallTo(CLI);
}
Modified: vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
==============================================================================
--- vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -177,25 +177,30 @@ bool RuntimeDyldMachO::isCompatibleFile(
}
template <typename Impl>
-void RuntimeDyldMachOCRTPBase<Impl>::finalizeLoad(const ObjectFile &ObjImg,
+void RuntimeDyldMachOCRTPBase<Impl>::finalizeLoad(const ObjectFile &Obj,
ObjSectionToIDMap &SectionMap) {
unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID;
unsigned TextSID = RTDYLD_INVALID_SECTION_ID;
unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID;
- ObjSectionToIDMap::iterator i, e;
- for (i = SectionMap.begin(), e = SectionMap.end(); i != e; ++i) {
- const SectionRef &Section = i->first;
+ for (const auto &Section : Obj.sections()) {
StringRef Name;
Section.getName(Name);
- if (Name == "__eh_frame")
- EHFrameSID = i->second;
- else if (Name == "__text")
- TextSID = i->second;
+
+ // Force emission of the __text, __eh_frame, and __gcc_except_tab sections
+ // if they're present. Otherwise call down to the impl to handle other
+ // sections that have already been emitted.
+ if (Name == "__text")
+ TextSID = findOrEmitSection(Obj, Section, true, SectionMap);
+ else if (Name == "__eh_frame")
+ EHFrameSID = findOrEmitSection(Obj, Section, false, SectionMap);
else if (Name == "__gcc_except_tab")
- ExceptTabSID = i->second;
- else
- impl().finalizeSection(ObjImg, i->second, Section);
+ ExceptTabSID = findOrEmitSection(Obj, Section, true, SectionMap);
+ else {
+ auto I = SectionMap.find(Section);
+ if (I != SectionMap.end())
+ impl().finalizeSection(Obj, I->second, Section);
+ }
}
UnregisteredEHFrameSections.push_back(
EHFrameRelatedSections(EHFrameSID, TextSID, ExceptTabSID));
@@ -238,7 +243,8 @@ unsigned char *RuntimeDyldMachOCRTPBase<
}
static int64_t computeDelta(SectionEntry *A, SectionEntry *B) {
- int64_t ObjDistance = A->ObjAddress - B->ObjAddress;
+ int64_t ObjDistance =
+ static_cast<int64_t>(A->ObjAddress) - static_cast<int64_t>(B->ObjAddress);
int64_t MemDistance = A->LoadAddress - B->LoadAddress;
return ObjDistance - MemDistance;
}
Modified: vendor/llvm/dist/lib/IR/ConstantFold.cpp
==============================================================================
--- vendor/llvm/dist/lib/IR/ConstantFold.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/IR/ConstantFold.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -1120,27 +1120,18 @@ Constant *llvm::ConstantFoldBinaryInstru
return ConstantInt::get(CI1->getContext(), C1V | C2V);
case Instruction::Xor:
return ConstantInt::get(CI1->getContext(), C1V ^ C2V);
- case Instruction::Shl: {
- uint32_t shiftAmt = C2V.getZExtValue();
- if (shiftAmt < C1V.getBitWidth())
- return ConstantInt::get(CI1->getContext(), C1V.shl(shiftAmt));
- else
- return UndefValue::get(C1->getType()); // too big shift is undef
- }
- case Instruction::LShr: {
- uint32_t shiftAmt = C2V.getZExtValue();
- if (shiftAmt < C1V.getBitWidth())
- return ConstantInt::get(CI1->getContext(), C1V.lshr(shiftAmt));
- else
- return UndefValue::get(C1->getType()); // too big shift is undef
- }
- case Instruction::AShr: {
- uint32_t shiftAmt = C2V.getZExtValue();
- if (shiftAmt < C1V.getBitWidth())
- return ConstantInt::get(CI1->getContext(), C1V.ashr(shiftAmt));
- else
- return UndefValue::get(C1->getType()); // too big shift is undef
- }
+ case Instruction::Shl:
+ if (C2V.ult(C1V.getBitWidth()))
+ return ConstantInt::get(CI1->getContext(), C1V.shl(C2V));
+ return UndefValue::get(C1->getType()); // too big shift is undef
+ case Instruction::LShr:
+ if (C2V.ult(C1V.getBitWidth()))
+ return ConstantInt::get(CI1->getContext(), C1V.lshr(C2V));
+ return UndefValue::get(C1->getType()); // too big shift is undef
+ case Instruction::AShr:
+ if (C2V.ult(C1V.getBitWidth()))
+ return ConstantInt::get(CI1->getContext(), C1V.ashr(C2V));
+ return UndefValue::get(C1->getType()); // too big shift is undef
}
}
Modified: vendor/llvm/dist/lib/IR/GCOV.cpp
==============================================================================
--- vendor/llvm/dist/lib/IR/GCOV.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/IR/GCOV.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -263,10 +263,12 @@ bool GCOVFunction::readGCDA(GCOVBuffer &
// required to combine the edge counts that are contained in the GCDA file.
for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) {
// The last block is always reserved for exit block
- if (BlockNo >= Blocks.size()-1) {
+ if (BlockNo >= Blocks.size()) {
errs() << "Unexpected number of edges (in " << Name << ").\n";
return false;
}
+ if (BlockNo == Blocks.size() - 1)
+ errs() << "(" << Name << ") has arcs from exit block.\n";
GCOVBlock &Block = *Blocks[BlockNo];
for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End;
++EdgeNo) {
Modified: vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp
==============================================================================
--- vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -3636,21 +3636,27 @@ bool AsmParser::parseDirectiveSpace(Stri
}
/// parseDirectiveLEB128
-/// ::= (.sleb128 | .uleb128) expression
+/// ::= (.sleb128 | .uleb128) [ expression (, expression)* ]
bool AsmParser::parseDirectiveLEB128(bool Signed) {
checkForValidSection();
const MCExpr *Value;
- if (parseExpression(Value))
- return true;
+ for (;;) {
+ if (parseExpression(Value))
+ return true;
- if (getLexer().isNot(AsmToken::EndOfStatement))
- return TokError("unexpected token in directive");
+ if (Signed)
+ getStreamer().EmitSLEB128Value(Value);
+ else
+ getStreamer().EmitULEB128Value(Value);
- if (Signed)
- getStreamer().EmitSLEB128Value(Value);
- else
- getStreamer().EmitULEB128Value(Value);
+ if (getLexer().is(AsmToken::EndOfStatement))
+ break;
+
+ if (getLexer().isNot(AsmToken::Comma))
+ return TokError("unexpected token in directive");
+ Lex();
+ }
return false;
}
Modified: vendor/llvm/dist/lib/Support/Unix/Memory.inc
==============================================================================
--- vendor/llvm/dist/lib/Support/Unix/Memory.inc Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Support/Unix/Memory.inc Thu May 21 06:57:07 2015 (r283176)
@@ -333,23 +333,12 @@ void Memory::InvalidateInstructionCache(
for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize)
asm volatile("icbi 0, %0" : : "r"(Line));
asm volatile("isync");
-# elif (defined(__arm__) || defined(__aarch64__)) && defined(__GNUC__)
+# elif (defined(__arm__) || defined(__aarch64__) || defined(__mips__)) && \
+ defined(__GNUC__)
// FIXME: Can we safely always call this for __GNUC__ everywhere?
const char *Start = static_cast<const char *>(Addr);
const char *End = Start + Len;
__clear_cache(const_cast<char *>(Start), const_cast<char *>(End));
-# elif defined(__mips__)
- const char *Start = static_cast<const char *>(Addr);
-# if defined(ANDROID)
- // The declaration of "cacheflush" in Android bionic:
- // extern int cacheflush(long start, long end, long flags);
- const char *End = Start + Len;
- long LStart = reinterpret_cast<long>(const_cast<char *>(Start));
- long LEnd = reinterpret_cast<long>(const_cast<char *>(End));
- cacheflush(LStart, LEnd, BCACHE);
-# else
- cacheflush(const_cast<char *>(Start), Len, BCACHE);
-# endif
# endif
#endif // end apple
Modified: vendor/llvm/dist/lib/Support/Windows/explicit_symbols.inc
==============================================================================
--- vendor/llvm/dist/lib/Support/Windows/explicit_symbols.inc Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Support/Windows/explicit_symbols.inc Thu May 21 06:57:07 2015 (r283176)
@@ -10,9 +10,15 @@
#ifdef HAVE___CHKSTK
EXPLICIT_SYMBOL(__chkstk)
#endif
+#ifdef HAVE___CHKSTK_MS
+ EXPLICIT_SYMBOL(__chkstk_ms)
+#endif
#ifdef HAVE____CHKSTK
EXPLICIT_SYMBOL(___chkstk)
#endif
+#ifdef HAVE____CHKSTK_MS
+ EXPLICIT_SYMBOL(___chkstk_ms)
+#endif
#ifdef HAVE___MAIN
EXPLICIT_SYMBOL(__main) // FIXME: Don't call it.
#endif
Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Target/AArch64/AArch64AsmPrinter.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -12,6 +12,8 @@
//
//===----------------------------------------------------------------------===//
+#include "MCTargetDesc/AArch64AddressingModes.h"
+#include "MCTargetDesc/AArch64MCExpr.h"
#include "AArch64.h"
#include "AArch64MCInstLower.h"
#include "AArch64MachineFunctionInfo.h"
@@ -494,24 +496,57 @@ void AArch64AsmPrinter::EmitInstruction(
EmitToStreamer(OutStreamer, TmpInst);
return;
}
- case AArch64::TLSDESC_BLR: {
- MCOperand Callee, Sym;
- MCInstLowering.lowerOperand(MI->getOperand(0), Callee);
- MCInstLowering.lowerOperand(MI->getOperand(1), Sym);
+ case AArch64::TLSDESC_CALLSEQ: {
+ /// lower this to:
+ /// adrp x0, :tlsdesc:var
+ /// ldr x1, [x0, #:tlsdesc_lo12:var]
+ /// add x0, x0, #:tlsdesc_lo12:var
+ /// .tlsdesccall var
+ /// blr x1
+ /// (TPIDR_EL0 offset now in x0)
+ const MachineOperand &MO_Sym = MI->getOperand(0);
+ MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
+ MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
+ MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
+ AArch64II::MO_NC);
+ MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
+ MCInstLowering.lowerOperand(MO_Sym, Sym);
+ MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
+ MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
+
+ MCInst Adrp;
+ Adrp.setOpcode(AArch64::ADRP);
+ Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Adrp.addOperand(SymTLSDesc);
+ EmitToStreamer(OutStreamer, Adrp);
+
+ MCInst Ldr;
+ Ldr.setOpcode(AArch64::LDRXui);
+ Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
+ Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Ldr.addOperand(SymTLSDescLo12);
+ Ldr.addOperand(MCOperand::CreateImm(0));
+ EmitToStreamer(OutStreamer, Ldr);
+
+ MCInst Add;
+ Add.setOpcode(AArch64::ADDXri);
+ Add.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Add.addOperand(MCOperand::CreateReg(AArch64::X0));
+ Add.addOperand(SymTLSDescLo12);
+ Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
+ EmitToStreamer(OutStreamer, Add);
- // First emit a relocation-annotation. This expands to no code, but requests
+ // Emit a relocation-annotation. This expands to no code, but requests
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
MCInst TLSDescCall;
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
TLSDescCall.addOperand(Sym);
EmitToStreamer(OutStreamer, TLSDescCall);
- // Other than that it's just a normal indirect call to the function loaded
- // from the descriptor.
- MCInst BLR;
- BLR.setOpcode(AArch64::BLR);
- BLR.addOperand(Callee);
- EmitToStreamer(OutStreamer, BLR);
+ MCInst Blr;
+ Blr.setOpcode(AArch64::BLR);
+ Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
+ EmitToStreamer(OutStreamer, Blr);
return;
}
Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -62,10 +62,10 @@ struct LDTLSCleanup : public MachineFunc
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
++I) {
switch (I->getOpcode()) {
- case AArch64::TLSDESC_BLR:
+ case AArch64::TLSDESC_CALLSEQ:
// Make sure it's a local dynamic access.
- if (!I->getOperand(1).isSymbol() ||
- strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
+ if (!I->getOperand(0).isSymbol() ||
+ strcmp(I->getOperand(0).getSymbolName(), "_TLS_MODULE_BASE_"))
break;
if (TLSBaseAddrReg)
Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp
==============================================================================
--- vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp Thu May 21 06:56:35 2015 (r283175)
+++ vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp Thu May 21 06:57:07 2015 (r283176)
@@ -64,8 +64,16 @@ EnableAArch64ExtrGeneration("aarch64-ext
static cl::opt<bool>
EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
- cl::desc("Allow AArch64 SLI/SRI formation"),
- cl::init(false));
+ cl::desc("Allow AArch64 SLI/SRI formation"),
+ cl::init(false));
+
+// FIXME: The necessary dtprel relocations don't seem to be supported
+// well in the GNU bfd and gold linkers at the moment. Therefore, by
+// default, for now, fall back to GeneralDynamic code generation.
+cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
+ "aarch64-elf-ldtls-generation", cl::Hidden,
+ cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
+ cl::init(false));
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
@@ -760,7 +768,7 @@ const char *AArch64TargetLowering::getTa
case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
- case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
+ case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
case AArch64ISD::ADC: return "AArch64ISD::ADC";
case AArch64ISD::SBC: return "AArch64ISD::SBC";
case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
@@ -2023,18 +2031,19 @@ SDValue AArch64TargetLowering::LowerForm
unsigned CurArgIdx = 0;
for (unsigned i = 0; i != NumArgs; ++i) {
MVT ValVT = Ins[i].VT;
- std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
- CurArgIdx = Ins[i].OrigArgIndex;
-
- // Get type of the original argument.
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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