svn commit: r225920 - user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416

[Adrian Chadd]

Author: adrian
Date: Sun Oct  2 13:29:29 2011
New Revision: 225920
URL: http://svn.freebsd.org/changeset/base/225920

Log:
  Interrupt fixups:
  
  * Remove the RAC versions of things - it's very unlikely I'll
    enable it for any of the ar5416 -> ar9287 chips.
  * Other slight tidyups

Modified:
  user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c

Modified: user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
==============================================================================
--- user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c	Sun Oct  2 12:18:06 2011	(r225919)
+++ user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c	Sun Oct  2 13:29:29 2011	(r225920)
@@ -70,6 +70,9 @@ ar5416GetPendingInterrupts(struct ath_ha
 	uint32_t isr, isr0, isr1, sync_cause = 0;
 	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
 
+	/*
+	 * Blank the interrupt debugging area regardless.
+	 */
 	bzero(&ah->ah_intrstate, sizeof(ah->ah_intrstate));
 
 	/*
@@ -122,21 +125,14 @@ ar5416GetPendingInterrupts(struct ath_ha
 			if (isr2 & AR_ISR_S2_TSFOOR)
 				mask2 |= HAL_INT_TSFOOR;
 
-			/* XXX TXURN? */
-
 			/*
 			 * Don't mask out AR_BCNMISC; instead mask
 			 * out what causes it.
 			 */
-			if (! pCap->halUseIsrRac) {
-				OS_REG_WRITE(ah, AR_ISR_S2, isr2);
-				isr &= ~AR_ISR_BCNMISC;
-			}
+			OS_REG_WRITE(ah, AR_ISR_S2, isr2);
+			isr &= ~AR_ISR_BCNMISC;
 		}
 
-		if (pCap->halUseIsrRac)
-			isr = OS_REG_READ(ah, AR_ISR_RAC);
-
 		if (isr == 0xffffffff) {
 			*masked = 0;
 			return AH_FALSE;
@@ -144,12 +140,10 @@ ar5416GetPendingInterrupts(struct ath_ha
 
 		*masked = isr & HAL_INT_COMMON;
 
-		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) {
+		if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
 			*masked |= HAL_INT_RX;
-		}
-		if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) {
+		if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
 			*masked |= HAL_INT_TX;
-		}
 
 		/*
 		 * When doing RX interrupt mitigation, the RXOK bit is set
@@ -171,25 +165,22 @@ ar5416GetPendingInterrupts(struct ath_ha
 			*masked |= HAL_INT_RX;
 #endif
 
-		if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) {
+		if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
+		    AR_ISR_TXEOL)) {
 			*masked |= HAL_INT_TX;
 
-			if (pCap->halUseIsrRac) {
-				isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
-				isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
-			} else {
-				isr0 = OS_REG_READ(ah, AR_ISR_S0);
-				OS_REG_WRITE(ah, AR_ISR_S0, isr0);
-				isr1 = OS_REG_READ(ah, AR_ISR_S1);
-				OS_REG_WRITE(ah, AR_ISR_S1, isr1);
-
-				/*
-				 * Don't clear the primary ISR TX bits, clear
-				 * what causes them (S0/S1.)
-				 */
-				isr &= ~(AR_ISR_TXOK | AR_ISR_TXDESC |
-				    AR_ISR_TXERR | AR_ISR_TXEOL);
-			}
+			isr0 = OS_REG_READ(ah, AR_ISR_S0);
+			OS_REG_WRITE(ah, AR_ISR_S0, isr0);
+			isr1 = OS_REG_READ(ah, AR_ISR_S1);
+			OS_REG_WRITE(ah, AR_ISR_S1, isr1);
+
+			/*
+			 * Don't clear the primary ISR TX bits, clear
+			 * what causes them (S0/S1.)
+			 */
+			isr &= ~(AR_ISR_TXOK | AR_ISR_TXDESC |
+			    AR_ISR_TXERR | AR_ISR_TXEOL);
+
 			ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
 			ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
 			ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
@@ -198,13 +189,10 @@ ar5416GetPendingInterrupts(struct ath_ha
 
 		if ((isr & AR_ISR_GENTMR) || (! pCap->halAutoSleepSupport)) {
 			uint32_t isr5;
-			if (pCap->halUseIsrRac) {
-				isr5 = OS_REG_READ(ah, AR_ISR_S5_S);
-			} else {
-				isr5 = OS_REG_READ(ah, AR_ISR_S5);
-				OS_REG_WRITE(ah, AR_ISR_S5, isr5);
-				isr &= ~AR_ISR_GENTMR;
-			}
+			isr5 = OS_REG_READ(ah, AR_ISR_S5);
+			OS_REG_WRITE(ah, AR_ISR_S5, isr5);
+			isr &= ~AR_ISR_GENTMR;
+
 			if (! pCap->halAutoSleepSupport)
 				if (isr5 & AR_ISR_S5_TIM_TIMER)
 					*masked |= HAL_INT_TIM_TIMER;
@@ -212,20 +200,18 @@ ar5416GetPendingInterrupts(struct ath_ha
 		*masked |= mask2;
 	}
 
-	if (! pCap->halUseIsrRac) {
-		/*
-		 * If we're not using AR_ISR_RAC, clear the status bits
-		 * for handled interrupts here. For bits whose interrupt
-		 * source is a secondary register, those bits should've been
-		 * masked out - instead of those bits being written back,
-		 * their source (ie, the secondary status registers) should
-		 * be cleared. That way there are no race conditions with
-		 * new triggers coming in whilst they've been read/cleared.
-		 */
-		OS_REG_WRITE(ah, AR_ISR, isr);
-		/* Flush previous write */
-		OS_REG_READ(ah, AR_ISR);
-	}
+	/*
+	 * Since we're not using AR_ISR_RAC, clear the status bits
+	 * for handled interrupts here. For bits whose interrupt
+	 * source is a secondary register, those bits should've been
+	 * masked out - instead of those bits being written back,
+	 * their source (ie, the secondary status registers) should
+	 * be cleared. That way there are no race conditions with
+	 * new triggers coming in whilst they've been read/cleared.
+	 */
+	OS_REG_WRITE(ah, AR_ISR, isr);
+	/* Flush previous write */
+	OS_REG_READ(ah, AR_ISR);
 
 	if (AR_SREV_HOWL(ah))
 		return AH_TRUE;