svn commit: r205783 - in user/jmallett/octeon/sys/mips: include mips
Juli Mallett
jmallett at FreeBSD.org
Sun Mar 28 00:58:21 UTC 2010
Author: jmallett
Date: Sun Mar 28 00:58:19 2010
New Revision: 205783
URL: http://svn.freebsd.org/changeset/base/205783
Log:
o) Push XKPHYS stuff into pmap aggressively.
o) Fix some pointer-width issues in exception.S and use <machine/asm.h>'s macros
for things rather than file-local ones.
o) Go back to making the PDE entries pointers for now.
Modified:
user/jmallett/octeon/sys/mips/include/cpuregs.h
user/jmallett/octeon/sys/mips/include/pte.h
user/jmallett/octeon/sys/mips/mips/exception.S
user/jmallett/octeon/sys/mips/mips/locore.S
user/jmallett/octeon/sys/mips/mips/pmap.c
Modified: user/jmallett/octeon/sys/mips/include/cpuregs.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpuregs.h Sun Mar 28 00:33:55 2010 (r205782)
+++ user/jmallett/octeon/sys/mips/include/cpuregs.h Sun Mar 28 00:58:19 2010 (r205783)
@@ -103,6 +103,9 @@
#define MIPS_KSEG2_START MIPS_KSSEG_START
#define MIPS_KSEG2_END MIPS_KSSEG_END
+#define MIPS_XKPHYS_START 0x8000000000000000
+#define MIPS_XKPHYS_END 0xbfffffffffffffff
+
#define MIPS_XKPHYS_CCA_UC 0x02 /* Uncached. */
#define MIPS_XKPHYS_CCA_CNC 0x03 /* Cacheable non-coherent. */
Modified: user/jmallett/octeon/sys/mips/include/pte.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pte.h Sun Mar 28 00:33:55 2010 (r205782)
+++ user/jmallett/octeon/sys/mips/include/pte.h Sun Mar 28 00:58:19 2010 (r205783)
@@ -84,7 +84,7 @@ struct tlb {
};
typedef int32_t pt_entry_t;
-typedef int32_t pd_entry_t;
+typedef pt_entry_t *pd_entry_t;
#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S Sun Mar 28 00:33:55 2010 (r205782)
+++ user/jmallett/octeon/sys/mips/mips/exception.S Sun Mar 28 00:58:19 2010 (r205783)
@@ -77,26 +77,12 @@
#endif
#ifdef WITH_64BIT_CP0
-#define _SLL dsll
-#define _SRL dsrl
-#define _MFC0 dmfc0
-#define _MTC0 dmtc0
#define WIRED_SHIFT 34
#else
-#define _SLL sll
-#define _SRL srl
-#define _MFC0 mfc0
-#define _MTC0 mtc0
#define WIRED_SHIFT 2
#endif
+
.set noreorder # Noreorder is default style!
-#if defined(ISA_MIPS32)
- .set mips32
-#elif defined(ISA_MIPS64)
- .set mips64
-#elif defined(ISA_MIPS3)
- .set mips3
-#endif
/*
* Reasonable limit
@@ -152,10 +138,13 @@ MipsDoTLBMiss:
GET_CPU_PCPU(k1)
PTR_L k1, PC_SEGBASE(k1)
beqz k1, 2f #05: make sure segbase is not null
+#if defined(__mips_n64)
+ andi k0, k0, 0x7f8 #06: k0=seg offset (mask 0x7)
+#else
andi k0, k0, 0x7fc #06: k0=seg offset (mask 0x3)
-#xxx mips64 unsafe?
+#endif
PTR_ADDU k1, k0, k1 #07: k1=seg entry address
- lw k1, 0(k1) #08: k1=seg entry
+ PTR_L k1, 0(k1) #08: k1=seg entry
mfc0 k0, COP_0_BAD_VADDR #09: k0=bad address (again)
beq k1, zero, 2f #0a: ==0 -- no page table
srl k0, PGSHIFT - 2 #0b: k0=VPN (aka va>>10)
@@ -165,12 +154,12 @@ MipsDoTLBMiss:
PTR_ADDU k1, k1, k0 #0d: k1=pte address
lw k0, 0(k1) #0e: k0=lo0 pte
lw k1, 4(k1) #0f: k1=lo1 pte
- _SLL k0, k0, WIRED_SHIFT #10: keep bottom 30 bits
- _SRL k0, k0, WIRED_SHIFT #11: keep bottom 30 bits
- _MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded
- _SLL k1, k1, WIRED_SHIFT #13: keep bottom 30 bits
- _SRL k1, k1, WIRED_SHIFT #14: keep bottom 30 bits
- _MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded
+ PTR_SLL k0, k0, WIRED_SHIFT #10: keep bottom 30 bits
+ PTR_SRL k0, k0, WIRED_SHIFT #11: keep bottom 30 bits
+ MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded
+ PTR_SLL k1, k1, WIRED_SHIFT #13: keep bottom 30 bits
+ PTR_SRL k1, k1, WIRED_SHIFT #14: keep bottom 30 bits
+ MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded
HAZARD_DELAY
tlbwr #1a: write to tlb
HAZARD_DELAY
@@ -341,7 +330,7 @@ SlowFault:
RESTORE_REG(t1, MULHI, sp) ;\
mtlo t0 ;\
mthi t1 ;\
- _MTC0 v0, COP_0_EXC_PC ;\
+ MTC0 v0, COP_0_EXC_PC ;\
.set noat ;\
RESTORE_REG(AT, AST, sp) ;\
RESTORE_REG(v0, V0, sp) ;\
@@ -545,7 +534,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM
mthi t1
RESTORE_U_PCB_REG(a0, PC, k1)
RESTORE_U_PCB_REG(v0, V0, k1)
- _MTC0 a0, COP_0_EXC_PC # set return address
+ MTC0 a0, COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
RESTORE_U_PCB_REG(a1, A1, k1)
@@ -789,7 +778,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r
RESTORE_U_PCB_REG(t2, PC, k1)
mtlo t0
mthi t1
- _MTC0 t2, COP_0_EXC_PC # set return address
+ MTC0 t2, COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v0, V0, k1)
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
@@ -849,9 +838,13 @@ NLEAF(MipsTLBInvalidException)
nop
srl k0, SEGSHIFT - 2
+#if defined(__mips_n64)
+ andi k0, 0xff8
+#else
andi k0, 0xffc
+#endif
PTR_ADDU k1, k1, k0
- lw k1, 0(k1)
+ PTR_L k1, 0(k1)
beqz k1, 3f /* invalid page table page pointer */
nop
@@ -871,28 +864,28 @@ NLEAF(MipsTLBInvalidException)
even_page:
lw k0, 0(k1)
- _SLL k0, k0, WIRED_SHIFT
- _SRL k0, k0, WIRED_SHIFT
- _MTC0 k0, COP_0_TLB_LO0
+ PTR_SLL k0, k0, WIRED_SHIFT
+ PTR_SRL k0, k0, WIRED_SHIFT
+ MTC0 k0, COP_0_TLB_LO0
lw k0, 4(k1)
- _SLL k0, k0, WIRED_SHIFT
- _SRL k0, k0, WIRED_SHIFT
- _MTC0 k0, COP_0_TLB_LO1
+ PTR_SLL k0, k0, WIRED_SHIFT
+ PTR_SRL k0, k0, WIRED_SHIFT
+ MTC0 k0, COP_0_TLB_LO1
b tlb_insert_entry
nop
odd_page:
lw k0, 0(k1)
- _SLL k0, k0, WIRED_SHIFT
- _SRL k0, k0, WIRED_SHIFT
- _MTC0 k0, COP_0_TLB_LO1
+ PTR_SLL k0, k0, WIRED_SHIFT
+ PTR_SRL k0, k0, WIRED_SHIFT
+ MTC0 k0, COP_0_TLB_LO1
lw k0, -4(k1)
- _SLL k0, k0, WIRED_SHIFT
- _SRL k0, k0, WIRED_SHIFT
- _MTC0 k0, COP_0_TLB_LO0
+ PTR_SLL k0, k0, WIRED_SHIFT
+ PTR_SRL k0, k0, WIRED_SHIFT
+ MTC0 k0, COP_0_TLB_LO0
tlb_insert_entry:
tlbp
@@ -1012,10 +1005,13 @@ NLEAF(MipsTLBMissException)
srl k0, 20 # k0=seg offset (almost)
PTR_L k1, %lo(_C_LABEL(kernel_segmap))(k1) # k1=segment tab base
beq k1, zero, _C_LABEL(MipsKernGenException) # ==0 -- no seg tab
+#if defined(__mips_n64)
+ andi k0, k0, 0xff8 # k0=seg offset (mask 0x7)
+#else
andi k0, k0, 0xffc # k0=seg offset (mask 0x3)
-#xxx mips64 unsafe
+#endif
PTR_ADDU k1, k0, k1 # k1=seg entry address
- lw k1, 0(k1) # k1=seg entry
+ PTR_L k1, 0(k1) # k1=seg entry
mfc0 k0, COP_0_BAD_VADDR # k0=bad address (again)
beq k1, zero, _C_LABEL(MipsKernGenException) # ==0 -- no page table
srl k0, 10 # k0=VPN (aka va>>10)
@@ -1024,12 +1020,12 @@ NLEAF(MipsTLBMissException)
PTR_ADDU k1, k1, k0 # k1=pte address
lw k0, 0(k1) # k0=lo0 pte
lw k1, 4(k1) # k1=lo1 pte
- _SLL k0, WIRED_SHIFT # chop bits [31..30]
- _SRL k0, WIRED_SHIFT # chop bits [31..30]
- _MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded
- _SLL k1, WIRED_SHIFT # chop bits [31..30]
- _SRL k1, WIRED_SHIFT # chop bits [31..30]
- _MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded
+ PTR_SLL k0, WIRED_SHIFT # chop bits [31..30]
+ PTR_SRL k0, WIRED_SHIFT # chop bits [31..30]
+ MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded
+ PTR_SLL k1, WIRED_SHIFT # chop bits [31..30]
+ PTR_SRL k1, WIRED_SHIFT # chop bits [31..30]
+ MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded
HAZARD_DELAY
tlbwr # write to tlb
@@ -1196,10 +1192,10 @@ NESTED_NOPROFILE(MipsCacheException, KER
.mask 0x80000000, -4
PTR_LA k0, _C_LABEL(panic) # return to panic
PTR_LA a0, 9f # panicstr
- _MFC0 a1, COP_0_ERROR_PC
+ MFC0 a1, COP_0_ERROR_PC
mfc0 a2, COP_0_CACHE_ERR # 3rd arg cache error
- _MTC0 k0, COP_0_ERROR_PC # set return address
+ MTC0 k0, COP_0_ERROR_PC # set return address
mfc0 k0, COP_0_STATUS_REG # restore status
li k1, SR_DIAG_DE # ignore further errors
Modified: user/jmallett/octeon/sys/mips/mips/locore.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/locore.S Sun Mar 28 00:33:55 2010 (r205782)
+++ user/jmallett/octeon/sys/mips/mips/locore.S Sun Mar 28 00:58:19 2010 (r205783)
@@ -181,7 +181,7 @@ VECTOR(_locore, unknown)
PTR_L a0, TD_PCB(sp)
REG_LI t0, ~7
and a0, a0, t0
- subu sp, a0, CALLFRAME_SIZ
+ PTR_SUBU sp, a0, CALLFRAME_SIZ
jal _C_LABEL(mi_startup) # mi_startup(frame)
sw zero, CALLFRAME_SIZ - 8(sp) # Zero out old fp for debugger
Modified: user/jmallett/octeon/sys/mips/mips/pmap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pmap.c Sun Mar 28 00:33:55 2010 (r205782)
+++ user/jmallett/octeon/sys/mips/mips/pmap.c Sun Mar 28 00:58:19 2010 (r205783)
@@ -200,6 +200,7 @@ static void pmap_update_page_action(void
#endif
+#if !defined(__mips_n64)
struct local_sysmaps {
struct mtx lock;
pt_entry_t CMAP1;
@@ -218,6 +219,7 @@ struct local_sysmaps {
*/
static struct local_sysmaps sysmap_lmem[MAXCPU];
caddr_t virtual_sys_start = (caddr_t)0;
+#endif
pt_entry_t *
pmap_segmap(pmap_t pmap, vm_offset_t va)
@@ -274,10 +276,14 @@ pmap_steal_memory(vm_size_t size)
pa = phys_avail[0];
phys_avail[0] += size;
+#if defined(__mips_n64)
+ va = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, pa);
+#else
if (pa >= MIPS_KSEG0_LARGEST_PHYS) {
panic("Out of memory below 512Meg?");
}
va = MIPS_PHYS_TO_KSEG0(pa);
+#endif
bzero((caddr_t)va, size);
return va;
}
@@ -292,7 +298,9 @@ pmap_bootstrap(void)
pt_entry_t *pgtab;
pt_entry_t *pte;
int i, j;
+#if !defined(__mips_n64)
int memory_larger_than_512meg = 0;
+#endif
/* Sort. */
again:
@@ -303,9 +311,11 @@ again:
phys_avail[i] = round_page(phys_avail[i]);
phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
+#if !defined(__mips_n64)
if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) {
memory_larger_than_512meg++;
}
+#endif
if (i < 2)
continue;
if (phys_avail[i - 2] > phys_avail[i]) {
@@ -381,6 +391,7 @@ again:
printf("pcpu is available at virtual address %p.\n", pcpup);
#endif
+#if !defined(__mips_n64)
/*
* Steal some virtual space that will not be in kernel_segmap. This
* va memory space will be used to map in kernel pages that are
@@ -401,6 +412,7 @@ again:
}
}
virtual_sys_start = (caddr_t)virtual_avail;
+#endif
/*
* Allocate segment table for the kernel
*/
@@ -410,6 +422,7 @@ again:
* Allocate second level page tables for the kernel
*/
nkpt = NKPT;
+#if !defined(__mips_n64)
if (memory_larger_than_512meg) {
/*
* If we have a large memory system we CANNOT afford to hit
@@ -426,6 +439,7 @@ again:
*/
nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - pmap_segshift(virtual_avail);
}
+#endif
pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt);
/*
@@ -1075,6 +1089,9 @@ pmap_pinit(pmap_t pmap)
ptdpg->valid = VM_PAGE_BITS_ALL;
ptdpa = VM_PAGE_TO_PHYS(ptdpg);
+#if defined(__mips_n64)
+ ptdva = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, ptdpa);
+#else
if (ptdpa < MIPS_KSEG0_LARGEST_PHYS) {
ptdva = MIPS_PHYS_TO_KSEG0(ptdpa);
} else {
@@ -1083,6 +1100,7 @@ pmap_pinit(pmap_t pmap)
panic("pmap_pinit: unable to allocate kva");
pmap_kenter(ptdva, ptdpa);
}
+#endif
pmap->pm_segtab = (pd_entry_t *)ptdva;
if ((ptdpg->flags & PG_ZERO) == 0)
@@ -1151,6 +1169,9 @@ _pmap_allocpte(pmap_t pmap, unsigned pte
pmap->pm_stats.resident_count++;
ptepa = VM_PAGE_TO_PHYS(m);
+#if defined(__mips_n64)
+ pteva = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, ptepa);
+#else
if (ptepa < MIPS_KSEG0_LARGEST_PHYS) {
pteva = MIPS_PHYS_TO_KSEG0(ptepa);
} else {
@@ -1159,6 +1180,7 @@ _pmap_allocpte(pmap_t pmap, unsigned pte
panic("_pmap_allocpte: unable to allocate kva");
pmap_kenter(pteva, ptepa);
}
+#endif
pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva;
@@ -1329,6 +1351,9 @@ pmap_growkernel(vm_offset_t addr)
nkpt++;
ptppaddr = VM_PAGE_TO_PHYS(nkpg);
+#if defined(__mips_n64)
+ pte = (pt_entry_t *)MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, ptppaddr);
+#else
if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) {
/*
* We need to do something here, but I am not sure
@@ -1341,7 +1366,8 @@ pmap_growkernel(vm_offset_t addr)
panic("Gak, can't handle a k-page table outside of lower 512Meg");
}
pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr);
- segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)(intptr_t)pte;
+#endif
+ segtab_pde(kernel_segmap, kernel_vm_end) = pte;
/*
* The R[4-7]?00 stores only one copy of the Global bit in
@@ -2160,7 +2186,9 @@ void *
pmap_kenter_temporary(vm_paddr_t pa, int i)
{
vm_offset_t va;
+#if !defined(__mips_n64)
int int_level;
+#endif
if (i != 0)
printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
__func__);
@@ -2171,6 +2199,9 @@ pmap_kenter_temporary(vm_paddr_t pa, int
TRUE);
} else
#endif
+#if defined(__mips_n64)
+ va = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, pa);
+#else
if (pa < MIPS_KSEG0_LARGEST_PHYS) {
va = MIPS_PHYS_TO_KSEG0(pa);
} else {
@@ -2191,12 +2222,14 @@ pmap_kenter_temporary(vm_paddr_t pa, int
va = (vm_offset_t)sysm->CADDR1;
restoreintr(int_level);
}
+#endif
return ((void *)va);
}
void
pmap_kenter_temporary_free(vm_paddr_t pa)
{
+#if !defined(__mips_n64)
int cpu;
int int_level;
struct local_sysmaps *sysm;
@@ -2214,6 +2247,7 @@ pmap_kenter_temporary_free(vm_paddr_t pa
sysm->CMAP1 = 0;
sysm->valid1 = 0;
}
+#endif
}
/*
@@ -2321,7 +2355,9 @@ pmap_zero_page(vm_page_t m)
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+#if !defined(__mips_n64)
int int_level;
+#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
struct fpage *fp1;
@@ -2342,6 +2378,14 @@ pmap_zero_page(vm_page_t m)
*/
} else
#endif
+#if defined(__mips_n64)
+ {
+ va = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ }
+#else
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
va = MIPS_PHYS_TO_KSEG0(phys);
@@ -2368,7 +2412,7 @@ pmap_zero_page(vm_page_t m)
sched_unpin();
PMAP_LGMEM_UNLOCK(sysm);
}
-
+#endif
}
/*
@@ -2382,7 +2426,9 @@ pmap_zero_page_area(vm_page_t m, int off
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+#if !defined(__mips_n64)
int int_level;
+#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
struct fpage *fp1;
@@ -2401,6 +2447,13 @@ pmap_zero_page_area(vm_page_t m, int off
mtx_unlock(&sysmaps->lock);
} else
#endif
+#if defined(__mips_n64)
+ {
+ va = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phys);
+ bzero((char *)(caddr_t)va + off, size);
+ mips_dcache_wbinv_range(va + off, size);
+ }
+#else
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
va = MIPS_PHYS_TO_KSEG0(phys);
bzero((char *)(caddr_t)va + off, size);
@@ -2425,6 +2478,7 @@ pmap_zero_page_area(vm_page_t m, int off
sched_unpin();
PMAP_LGMEM_UNLOCK(sysm);
}
+#endif
}
void
@@ -2432,7 +2486,9 @@ pmap_zero_page_idle(vm_page_t m)
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+#if !defined(__mips_n64)
int int_level;
+#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
sched_pin();
@@ -2442,6 +2498,13 @@ pmap_zero_page_idle(vm_page_t m)
sched_unpin();
} else
#endif
+#if defined(__mips_n64)
+ {
+ va = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+ }
+#else
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
va = MIPS_PHYS_TO_KSEG0(phys);
bzero((caddr_t)va, PAGE_SIZE);
@@ -2466,7 +2529,7 @@ pmap_zero_page_idle(vm_page_t m)
sched_unpin();
PMAP_LGMEM_UNLOCK(sysm);
}
-
+#endif
}
/*
@@ -2481,7 +2544,9 @@ pmap_copy_page(vm_page_t src, vm_page_t
vm_offset_t va_src, va_dst;
vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src);
vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst);
+#if !defined(__mips_n64)
int int_level;
+#endif
#ifdef VM_ALLOC_WIRED_TLB_PG_POOL
if (need_wired_tlb_page_pool) {
struct fpage *fp1, *fp2;
@@ -2510,6 +2575,14 @@ pmap_copy_page(vm_page_t src, vm_page_t
} else
#endif
{
+#if defined(__mips_n64)
+ pmap_flush_pvcache(src);
+ mips_dcache_wbinv_range_index(MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_dst), NBPG);
+ va_src = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_src);
+ va_dst = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_dst);
+ bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
+ mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
+#else
if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) {
/* easy case, all can be accessed via KSEG0 */
/*
@@ -2571,6 +2644,7 @@ pmap_copy_page(vm_page_t src, vm_page_t
sched_unpin();
PMAP_LGMEM_UNLOCK(sysm);
}
+#endif
}
}
@@ -3323,17 +3397,24 @@ pmap_kextract(vm_offset_t va)
(va < (VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET))))
pa = MIPS_KSEG0_TO_PHYS(va);
#endif
+#if defined(__mips_n64)
+ else if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
+ pa = MIPS_XKPHYS_TO_PHYS(va);
+#endif
else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) {
pt_entry_t *ptep;
/* Is the kernel pmap initialized? */
if (kernel_pmap->pm_active) {
+#if !defined(__mips_n64)
if (va >= (vm_offset_t)virtual_sys_start) {
+#endif
/* Its inside the virtual address range */
ptep = pmap_pte(kernel_pmap, va);
if (ptep)
pa = mips_tlbpfn_to_paddr(*ptep) |
(va & PAGE_MASK);
+#if !defined(__mips_n64)
} else {
int i;
@@ -3356,6 +3437,7 @@ pmap_kextract(vm_offset_t va)
}
}
}
+#endif
}
}
return pa;
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