svn commit: r205545 - in user/jmallett/octeon/sys/mips: include mips
Juli Mallett
jmallett at FreeBSD.org
Tue Mar 23 22:06:57 UTC 2010
Author: jmallett
Date: Tue Mar 23 22:06:56 2010
New Revision: 205545
URL: http://svn.freebsd.org/changeset/base/205545
Log:
o) Move some stuff from <machine/param.h> to <machine/vmparam.h>.
o) Remove some gratuitous ISA setting in assembly files -- ISA must be set
properly in the compiler (and assembler.)
o) Use <machine/asm.h>'s ISA-dependent instruction wrappers rather than hand-
rolled versions in each assembly file.
o) Reflect the fact that our pmap is solidly 32-bit by making PTEs and PDEs
32-bits. This lets us go back to the old segmap sizing which uses a page
at a time rather than two pages at a time, which gives us a fighting chance
with n64 kernels.
Sponsored by: Packet Forensics
Modified:
user/jmallett/octeon/sys/mips/include/param.h
user/jmallett/octeon/sys/mips/include/pmap.h
user/jmallett/octeon/sys/mips/include/pte.h
user/jmallett/octeon/sys/mips/include/vmparam.h
user/jmallett/octeon/sys/mips/mips/pmap.c
user/jmallett/octeon/sys/mips/mips/support.S
user/jmallett/octeon/sys/mips/mips/swtch.S
user/jmallett/octeon/sys/mips/mips/tlb.S
user/jmallett/octeon/sys/mips/mips/trap.c
Modified: user/jmallett/octeon/sys/mips/include/param.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/param.h Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/include/param.h Tue Mar 23 22:06:56 2010 (r205545)
@@ -111,19 +111,8 @@
#define PAGE_MASK (PAGE_SIZE-1)
#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
-#define NBSEG 0x400000 /* bytes/segment */
-#define SEGOFSET (NBSEG-1) /* byte offset into segment */
-#define SEGSHIFT 22 /* LOG2(NBSEG) */
-
#define MAXPAGESIZES 1 /* maximum number of supported page sizes */
-/* XXXimp: This has moved to vmparam.h */
-/* Also, this differs from the mips2 definition, but likely is better */
-/* since this means the kernel won't chew up TLBs when it is executing */
-/* code */
-#define KERNBASE 0x80000000 /* start of kernel virtual */
-#define BTOPKERNBASE ((u_long)KERNBASE >> PGSHIFT)
-
#define BLKDEV_IOSIZE 2048 /* xxx: Why is this 1/2 page? */
#define MAXDUMPPGS 1 /* xxx: why is this only one? */
Modified: user/jmallett/octeon/sys/mips/include/pmap.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pmap.h Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/include/pmap.h Tue Mar 23 22:06:56 2010 (r205545)
@@ -100,7 +100,7 @@ typedef struct pmap *pmap_t;
#ifdef _KERNEL
pt_entry_t *pmap_pte(pmap_t, vm_offset_t);
-pd_entry_t pmap_segmap(pmap_t pmap, vm_offset_t va);
+pt_entry_t *pmap_segmap(pmap_t pmap, vm_offset_t va);
vm_offset_t pmap_kextract(vm_offset_t va);
#define vtophys(va) pmap_kextract(((vm_offset_t) (va)))
Modified: user/jmallett/octeon/sys/mips/include/pte.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pte.h Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/include/pte.h Tue Mar 23 22:06:56 2010 (r205545)
@@ -83,8 +83,8 @@ struct tlb {
int tlb_lo1;
};
-typedef unsigned long pt_entry_t;
-typedef pt_entry_t *pd_entry_t;
+typedef int32_t pt_entry_t;
+typedef int32_t pd_entry_t;
#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
Modified: user/jmallett/octeon/sys/mips/include/vmparam.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/vmparam.h Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/include/vmparam.h Tue Mar 23 22:06:56 2010 (r205545)
@@ -108,6 +108,11 @@
#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)(intptr_t)(int32_t)0xC0000000)
#define VM_KERNEL_WIRED_ADDR_END (VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET)
#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)(intptr_t)(int32_t)0xFFFFC000)
+#if 0
+#define KERNBASE (VM_MIN_KERNEL_ADDRESS)
+#else
+#define KERNBASE ((vm_offset_t)(intptr_t)(int32_t)0x80000000)
+#endif
/*
* Disable superpage reservations. (not sure if this is right
@@ -179,21 +184,6 @@
*/
#define VM_NFREEORDER 9
-/*
- * XXXMIPS: This values need to be changed!!!
- */
-#if 0
-#define VM_MIN_ADDRESS ((vm_offset_t)0x0000000000010000)
-#define VM_MAXUSER_ADDRESS ((vm_offset_t)MIPS_KSEG0_START-1)
-#define VM_MAX_ADDRESS ((vm_offset_t)0x0000000100000000)
-#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)MIPS_KSEG3_START)
-#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)MIPS_KSEG3_END)
-#define KERNBASE (VM_MIN_KERNEL_ADDRESS)
-
-/* virtual sizes (bytes) for various kernel submaps */
-#define VM_KMEM_SIZE (16*1024*1024) /* XXX ??? */
-#endif
-
#define NBSEG 0x400000 /* bytes/segment */
#define SEGOFSET (NBSEG-1) /* byte offset into segment */
#define SEGSHIFT 22 /* LOG2(NBSEG) */
Modified: user/jmallett/octeon/sys/mips/mips/pmap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pmap.c Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/mips/pmap.c Tue Mar 23 22:06:56 2010 (r205545)
@@ -219,11 +219,11 @@ struct local_sysmaps {
static struct local_sysmaps sysmap_lmem[MAXCPU];
caddr_t virtual_sys_start = (caddr_t)0;
-pd_entry_t
+pt_entry_t *
pmap_segmap(pmap_t pmap, vm_offset_t va)
{
if (pmap->pm_segtab)
- return (*pmap_pde(pmap, va));
+ return ((pt_entry_t *)(intptr_t)*pmap_pde(pmap, va));
else
return ((pd_entry_t)0);
}
@@ -240,7 +240,7 @@ pmap_pte(pmap_t pmap, vm_offset_t va)
pt_entry_t *pdeaddr;
if (pmap) {
- pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va);
+ pdeaddr = pmap_segmap(pmap, va);
if (pdeaddr) {
return pdeaddr + vad_to_pte_offset(va);
}
@@ -424,9 +424,9 @@ again:
* be somewhere above 0xC0000000 - 0xFFFFFFFF which results
* in about 256 entries or so instead of the 120.
*/
- nkpt = ((PAGE_SIZE * 2) / sizeof(pd_entry_t)) - pmap_segshift(virtual_avail);
+ nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - pmap_segshift(virtual_avail);
}
- pgtab = (pt_entry_t *)pmap_steal_memory((PAGE_SIZE * 2) * nkpt);
+ pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt);
/*
* The R[4-7]?00 stores only one copy of the Global bit in the
@@ -443,7 +443,7 @@ again:
* level page table.
*/
for (i = 0, j = pmap_segshift(virtual_avail); i < nkpt; i++, j++)
- kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG));
+ kernel_segmap[j] = (pd_entry_t)(intptr_t)(pgtab + (i * NPTEPG));
/*
* The kernel's pmap is statically allocated so we don't have to use
@@ -1333,7 +1333,7 @@ pmap_growkernel(vm_offset_t addr)
panic("Gak, can't handle a k-page table outside of lower 512Meg");
}
pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr);
- segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte;
+ segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)(intptr_t)pte;
/*
* The R[4-7]?00 stores only one copy of the Global bit in
@@ -1990,7 +1990,7 @@ validate:
if (origpte & PTE_M) {
KASSERT((origpte & PTE_RW),
("pmap_enter: modified page not writable:"
- " va: %p, pte: 0x%lx", (void *)va, origpte));
+ " va: %p, pte: 0x%x", (void *)va, origpte));
if (page_is_managed(opa))
vm_page_dirty(om);
}
@@ -2636,7 +2636,7 @@ pmap_remove_pages(pmap_t pmap)
m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte));
KASSERT(m < &vm_page_array[vm_page_array_size],
- ("pmap_remove_pages: bad tpte %lx", tpte));
+ ("pmap_remove_pages: bad tpte %x", tpte));
pv->pv_pmap->pm_stats.resident_count--;
Modified: user/jmallett/octeon/sys/mips/mips/support.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/support.S Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/mips/support.S Tue Mar 23 22:06:56 2010 (r205545)
@@ -1290,9 +1290,6 @@ END(atomic_subtract_8)
*/
.set noreorder # Noreorder is default style!
-#ifndef _MIPS_ARCH_XLR
- .set mips3
-#endif
#if !defined(__mips_n64) && !defined(__mips_n32)
/*
Modified: user/jmallett/octeon/sys/mips/mips/swtch.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/swtch.S Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/mips/swtch.S Tue Mar 23 22:06:56 2010 (r205545)
@@ -65,37 +65,7 @@
#include "assym.s"
-#if defined(ISA_MIPS32)
-#undef WITH_64BIT_CP0
-#elif defined(ISA_MIPS64)
-#define WITH_64BIT_CP0
-#elif defined(ISA_MIPS3)
-#define WITH_64BIT_CP0
-#else
-#error "Please write the code for this ISA"
-#endif
-
-#ifdef WITH_64BIT_CP0
-#define _SLL dsll
-#define _SRL dsrl
-#define _MFC0 dmfc0
-#define _MTC0 dmtc0
-#define WIRED_SHIFT 34
-#else
-#define _SLL sll
-#define _SRL srl
-#define _MFC0 mfc0
-#define _MTC0 mtc0
-#define WIRED_SHIFT 2
-#endif
.set noreorder # Noreorder is default style!
-#if defined(ISA_MIPS32)
- .set mips32
-#elif defined(ISA_MIPS64)
- .set mips64
-#elif defined(ISA_MIPS3)
- .set mips3
-#endif
/*
* FREEBSD_DEVELOPERS_FIXME
@@ -165,7 +135,7 @@ LEAF(fork_trampoline)
RESTORE_U_PCB_REG(a0, PC, k1)
RESTORE_U_PCB_REG(AT, AST, k1)
RESTORE_U_PCB_REG(v0, V0, k1)
- _MTC0 a0, COP_0_EXC_PC # set return address
+ MTC0 a0, COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
Modified: user/jmallett/octeon/sys/mips/mips/tlb.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/tlb.S Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/mips/tlb.S Tue Mar 23 22:06:56 2010 (r205545)
@@ -76,26 +76,11 @@
#endif
#ifdef WITH_64BIT_CP0
-#define _SLL dsll
-#define _SRL dsrl
-#define _MFC0 dmfc0
-#define _MTC0 dmtc0
#define WIRED_SHIFT 34
#else
-#define _SLL sll
-#define _SRL srl
-#define _MFC0 mfc0
-#define _MTC0 mtc0
#define WIRED_SHIFT 2
#endif
.set noreorder # Noreorder is default style!
-#if defined(ISA_MIPS32)
- .set mips32
-#elif defined(ISA_MIPS64)
- .set mips64
-#elif defined(ISA_MIPS3)
- .set mips3
-#endif
#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
@@ -125,22 +110,22 @@ LEAF(Mips_TLBWriteIndexed)
ITLBNOPFIX
lw a2, 8(a1)
lw a3, 12(a1)
- _MFC0 t0, COP_0_TLB_HI # Save the current PID.
+ MFC0 t0, COP_0_TLB_HI # Save the current PID.
- _MTC0 a2, COP_0_TLB_LO0 # Set up entry low0.
- _MTC0 a3, COP_0_TLB_LO1 # Set up entry low1.
+ MTC0 a2, COP_0_TLB_LO0 # Set up entry low0.
+ MTC0 a3, COP_0_TLB_LO1 # Set up entry low1.
lw a2, 0(a1)
lw a3, 4(a1)
mtc0 a0, COP_0_TLB_INDEX # Set the index.
- _MTC0 a2, COP_0_TLB_PG_MASK # Set up entry mask.
- _MTC0 a3, COP_0_TLB_HI # Set up entry high.
+ MTC0 a2, COP_0_TLB_PG_MASK # Set up entry mask.
+ MTC0 a3, COP_0_TLB_HI # Set up entry high.
MIPS_CPU_NOP_DELAY
tlbwi # Write the TLB
MIPS_CPU_NOP_DELAY
- _MTC0 t0, COP_0_TLB_HI # Restore the PID.
+ MTC0 t0, COP_0_TLB_HI # Restore the PID.
nop
- _MTC0 zero, COP_0_TLB_PG_MASK # Default mask value.
+ MTC0 zero, COP_0_TLB_PG_MASK # Default mask value.
mtc0 v1, COP_0_STATUS_REG # Restore the status register
ITLBNOPFIX
j ra
@@ -162,7 +147,7 @@ END(Mips_TLBWriteIndexed)
*--------------------------------------------------------------------------
*/
LEAF(Mips_SetPID)
- _MTC0 a0, COP_0_TLB_HI # Write the hi reg value
+ MTC0 a0, COP_0_TLB_HI # Write the hi reg value
nop # required for QED5230
nop # required for QED5230
j ra
@@ -230,9 +215,9 @@ LEAF(Mips_TLBFlush)
mtc0 zero, COP_0_STATUS_REG # Disable interrupts
ITLBNOPFIX
mfc0 t1, COP_0_TLB_WIRED
- _MFC0 t0, COP_0_TLB_HI # Save the PID
- _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0.
- _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1.
+ MFC0 t0, COP_0_TLB_HI # Save the PID
+ MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0.
+ MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1.
mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry.
#
# Load invalid entry, each TLB entry should have it's own bogus
@@ -249,7 +234,7 @@ LEAF(Mips_TLBFlush)
1:
mtc0 t1, COP_0_TLB_INDEX # Set the index register.
ITLBNOPFIX
- _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid
+ MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid
addu t1, t1, 1 # Increment index.
addu v0, v0, 8 * 1024
MIPS_CPU_NOP_DELAY
@@ -257,7 +242,7 @@ LEAF(Mips_TLBFlush)
MIPS_CPU_NOP_DELAY
bne t1, a0, 1b
nop
- _MTC0 t0, COP_0_TLB_HI # Restore the PID
+ MTC0 t0, COP_0_TLB_HI # Restore the PID
mtc0 v1, COP_0_STATUS_REG # Restore the status register
ITLBNOPFIX
j ra
@@ -285,9 +270,9 @@ LEAF(Mips_TLBFlushAddr)
ITLBNOPFIX
li v0, (PTE_HVPN | PTE_ASID)
and a0, a0, v0 # Make shure valid hi value.
- _MFC0 t0, COP_0_TLB_HI # Get current PID
+ MFC0 t0, COP_0_TLB_HI # Get current PID
mfc0 t3, COP_0_TLB_PG_MASK # Save current pgMask
- _MTC0 a0, COP_0_TLB_HI # look for addr & PID
+ MTC0 a0, COP_0_TLB_HI # look for addr & PID
MIPS_CPU_NOP_DELAY
tlbp # Probe for the entry.
MIPS_CPU_NOP_DELAY
@@ -301,15 +286,15 @@ LEAF(Mips_TLBFlushAddr)
# One bogus value for every TLB entry might cause MCHECK exception
sll v0, PGSHIFT + 1
addu t1, v0
- _MTC0 t1, COP_0_TLB_HI # Mark entry high as invalid
+ MTC0 t1, COP_0_TLB_HI # Mark entry high as invalid
- _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry.
- _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry.
+ MTC0 zero, COP_0_TLB_LO0 # Zero out low entry.
+ MTC0 zero, COP_0_TLB_LO1 # Zero out low entry.
MIPS_CPU_NOP_DELAY
tlbwi
MIPS_CPU_NOP_DELAY
1:
- _MTC0 t0, COP_0_TLB_HI # restore PID
+ MTC0 t0, COP_0_TLB_HI # restore PID
mtc0 t3, COP_0_TLB_PG_MASK # Restore pgMask
mtc0 v1, COP_0_STATUS_REG # Restore the status register
ITLBNOPFIX
@@ -338,13 +323,13 @@ LEAF(Mips_TLBUpdate)
and t1, a0, 0x1000 # t1 = Even/Odd flag
li v0, (PTE_HVPN | PTE_ASID)
and a0, a0, v0
- _MFC0 t0, COP_0_TLB_HI # Save current PID
- _MTC0 a0, COP_0_TLB_HI # Init high reg
+ MFC0 t0, COP_0_TLB_HI # Save current PID
+ MTC0 a0, COP_0_TLB_HI # Init high reg
and a2, a1, PTE_G # Copy global bit
MIPS_CPU_NOP_DELAY
tlbp # Probe for the entry.
- _SLL a1, a1, WIRED_SHIFT
- _SRL a1, a1, WIRED_SHIFT
+ PTR_SLL a1, a1, WIRED_SHIFT
+ PTR_SRL a1, a1, WIRED_SHIFT
nop
mfc0 v0, COP_0_TLB_INDEX # See what we got
bne t1, zero, 2f # Decide even odd
@@ -355,16 +340,16 @@ LEAF(Mips_TLBUpdate)
tlbr # update, read entry first
MIPS_CPU_NOP_DELAY
- _MTC0 a1, COP_0_TLB_LO0 # init low reg0.
+ MTC0 a1, COP_0_TLB_LO0 # init low reg0.
MIPS_CPU_NOP_DELAY
tlbwi # update slot found
b 4f
nop
1:
mtc0 zero, COP_0_TLB_PG_MASK # init mask.
- _MTC0 a0, COP_0_TLB_HI # init high reg.
- _MTC0 a1, COP_0_TLB_LO0 # init low reg0.
- _MTC0 a2, COP_0_TLB_LO1 # init low reg1.
+ MTC0 a0, COP_0_TLB_HI # init high reg.
+ MTC0 a1, COP_0_TLB_LO0 # init low reg0.
+ MTC0 a2, COP_0_TLB_LO1 # init low reg1.
MIPS_CPU_NOP_DELAY
tlbwr # enter into a random slot
MIPS_CPU_NOP_DELAY
@@ -378,7 +363,7 @@ LEAF(Mips_TLBUpdate)
tlbr # read the entry first
MIPS_CPU_NOP_DELAY
- _MTC0 a1, COP_0_TLB_LO1 # init low reg1.
+ MTC0 a1, COP_0_TLB_LO1 # init low reg1.
MIPS_CPU_NOP_DELAY
tlbwi # update slot found
MIPS_CPU_NOP_DELAY
@@ -386,15 +371,15 @@ LEAF(Mips_TLBUpdate)
nop
3:
mtc0 zero, COP_0_TLB_PG_MASK # init mask.
- _MTC0 a0, COP_0_TLB_HI # init high reg.
- _MTC0 a2, COP_0_TLB_LO0 # init low reg0.
- _MTC0 a1, COP_0_TLB_LO1 # init low reg1.
+ MTC0 a0, COP_0_TLB_HI # init high reg.
+ MTC0 a2, COP_0_TLB_LO0 # init low reg0.
+ MTC0 a1, COP_0_TLB_LO1 # init low reg1.
MIPS_CPU_NOP_DELAY
tlbwr # enter into a random slot
4: # Make shure pipeline
MIPS_CPU_NOP_DELAY
- _MTC0 t0, COP_0_TLB_HI # restore PID
+ MTC0 t0, COP_0_TLB_HI # restore PID
mtc0 v1, COP_0_STATUS_REG # Restore the status register
ITLBNOPFIX
j ra
@@ -419,17 +404,17 @@ LEAF(Mips_TLBRead)
mfc0 v1, COP_0_STATUS_REG # Save the status register.
mtc0 zero, COP_0_STATUS_REG # Disable interrupts
ITLBNOPFIX
- _MFC0 t0, COP_0_TLB_HI # Get current PID
+ MFC0 t0, COP_0_TLB_HI # Get current PID
mtc0 a0, COP_0_TLB_INDEX # Set the index register
MIPS_CPU_NOP_DELAY
tlbr # Read from the TLB
MIPS_CPU_NOP_DELAY
mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry
- _MFC0 t3, COP_0_TLB_HI # fetch the hi entry
- _MFC0 ta0, COP_0_TLB_LO0 # See what we got
- _MFC0 ta1, COP_0_TLB_LO1 # See what we got
- _MTC0 t0, COP_0_TLB_HI # restore PID
+ MFC0 t3, COP_0_TLB_HI # fetch the hi entry
+ MFC0 ta0, COP_0_TLB_LO0 # See what we got
+ MFC0 ta1, COP_0_TLB_LO1 # See what we got
+ MTC0 t0, COP_0_TLB_HI # restore PID
MIPS_CPU_NOP_DELAY
mtc0 v1, COP_0_STATUS_REG # Restore the status register
ITLBNOPFIX
@@ -453,7 +438,7 @@ END(Mips_TLBRead)
*--------------------------------------------------------------------------
*/
LEAF(Mips_TLBGetPID)
- _MFC0 v0, COP_0_TLB_HI # get PID
+ MFC0 v0, COP_0_TLB_HI # get PID
j ra
and v0, v0, VMTLB_PID # mask off PID
END(Mips_TLBGetPID)
@@ -473,7 +458,7 @@ LEAF(mips_TBIAP)
mfc0 v1, COP_0_STATUS_REG # save status register
mtc0 zero, COP_0_STATUS_REG # disable interrupts
- _MFC0 ta0, COP_0_TLB_HI # Get current PID
+ MFC0 ta0, COP_0_TLB_HI # Get current PID
move t2, a0
mfc0 t1, COP_0_TLB_WIRED
#
@@ -494,14 +479,14 @@ LEAF(mips_TBIAP)
MIPS_CPU_NOP_DELAY
tlbr # obtain an entry
MIPS_CPU_NOP_DELAY
- _MFC0 a0, COP_0_TLB_LO1
+ MFC0 a0, COP_0_TLB_LO1
and a0, a0, PTE_G # check to see it has G bit
bnez a0, 2f
nop
- _MTC0 v0, COP_0_TLB_HI # make entryHi invalid
- _MTC0 zero, COP_0_TLB_LO0 # zero out entryLo0
- _MTC0 zero, COP_0_TLB_LO1 # zero out entryLo1
+ MTC0 v0, COP_0_TLB_HI # make entryHi invalid
+ MTC0 zero, COP_0_TLB_LO0 # zero out entryLo0
+ MTC0 zero, COP_0_TLB_LO1 # zero out entryLo1
mtc0 zero, COP_0_TLB_PG_MASK # zero out mask entry
MIPS_CPU_NOP_DELAY
tlbwi # invalidate the TLB entry
@@ -511,11 +496,10 @@ LEAF(mips_TBIAP)
bne t1, t2, 1b
nop
- _MTC0 ta0, COP_0_TLB_HI # restore PID
+ MTC0 ta0, COP_0_TLB_HI # restore PID
mtc0 t3, COP_0_TLB_PG_MASK # restore pgMask
MIPS_CPU_NOP_DELAY
mtc0 v1, COP_0_STATUS_REG # restore status register
j ra # new ASID will be set soon
nop
- .set mips2
END(mips_TBIAP)
Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c Tue Mar 23 22:04:18 2010 (r205544)
+++ user/jmallett/octeon/sys/mips/mips/trap.c Tue Mar 23 22:06:56 2010 (r205545)
@@ -1310,7 +1310,7 @@ get_mapping_info(vm_offset_t va, pd_entr
pd_entry_t *pdep;
struct proc *p = curproc;
- pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[va >> SEGSHIFT]));
+ pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(uint32_t)va >> SEGSHIFT]));
if (*pdep)
ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
else
@@ -1351,8 +1351,8 @@ log_illegal_instruction(const char *msg,
if (!(pc & 3) &&
useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
/* dump page table entry for faulting instruction */
- log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = 0x%lx\n",
- (intmax_t)pc, *pdep, ptep ? *ptep : 0);
+ log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#x\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0);
addr = (unsigned int *)(intptr_t)pc;
log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
@@ -1360,8 +1360,8 @@ log_illegal_instruction(const char *msg,
log(LOG_ERR, "%08x %08x %08x %08x\n",
addr[0], addr[1], addr[2], addr[3]);
} else {
- log(LOG_ERR, "pc address %#jx is inaccessible, pde = 0x%p, pte = 0x%lx\n",
- (intmax_t)pc, *pdep, ptep ? *ptep : 0);
+ log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#x\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0);
}
}
@@ -1415,8 +1415,8 @@ log_bad_page_fault(char *msg, struct tra
(trap_type != T_BUS_ERR_IFETCH) &&
useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
/* dump page table entry for faulting instruction */
- log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = 0x%lx\n",
- (intmax_t)pc, *pdep, ptep ? *ptep : 0);
+ log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#x\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0);
addr = (unsigned int *)(intptr_t)pc;
log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
@@ -1424,8 +1424,8 @@ log_bad_page_fault(char *msg, struct tra
log(LOG_ERR, "%08x %08x %08x %08x\n",
addr[0], addr[1], addr[2], addr[3]);
} else {
- log(LOG_ERR, "pc address %#jx is inaccessible, pde = 0x%p, pte = 0x%lx\n",
- (intmax_t)pc, *pdep, ptep ? *ptep : 0);
+ log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#x\n",
+ (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0);
}
/* panic("Bad trap");*/
}
More information about the svn-src-user
mailing list