svn commit: r205247 - user/jmallett/octeon/sys/mips/mips

[Juli Mallett]

Author: jmallett
Date: Wed Mar 17 08:55:29 2010
New Revision: 205247
URL: http://svn.freebsd.org/changeset/base/205247

Log:
  Enable 64-bit operations for threads as well.  There are a multitude of sins
  surrounding this that are not yet fixed, including:
  o) The multiple copies of status register and other coprocessor-related bits.
  o) The fact that all of these bits are spelled out here at all rather than
     included in some KERNEL_STATUS and USER_STATUS definitions.
  o) The fact that these things are under "TARGET_OCTEON" rather than something
     related to ABI, since the only thing that should restrict whether user
     programs can use 64-bit instructions is whether the kernel can save and
     restore 64-bit registers.
  o) The fact that many things here enable 64-bit virtual addresses for
     supervisor mode, which FreeBSD has never used (although we can and should
     consider repurposing those address spaces when the time is right.)
  o) All of the duplication of logic wrt setting up PCBs and trapframes in
     this file.  (To say nothing of the varying styles that makes it easy to
     miss these differences.)
  o) The lack of any assertions about the state of the status register for user
     threads with INVARIANTS on.
  
  Sponsored by:	Packet Forensics

Modified:
  user/jmallett/octeon/sys/mips/mips/vm_machdep.c

Modified: user/jmallett/octeon/sys/mips/mips/vm_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/vm_machdep.c	Wed Mar 17 07:26:59 2010	(r205246)
+++ user/jmallett/octeon/sys/mips/mips/vm_machdep.c	Wed Mar 17 08:55:29 2010	(r205247)
@@ -425,7 +425,7 @@ cpu_set_upcall_kse(struct thread *td, vo
 	tf->sr = SR_KSU_USER | SR_EXL | (SR_INT_MASK & mips_rd_status()) |
 	    MIPS_SR_INT_IE;
 #ifdef TARGET_OCTEON
-	tf->sr |=  MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_UX |
+	tf->sr |=  MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS32_SR_PX | MIPS_SR_UX |
 	  MIPS_SR_KX;
 #endif
 /*	tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */