svn commit: r205025 - user/jmallett/octeon/sys/mips/mips

[Robert Watson]

On Thu, 11 Mar 2010, Juli Mallett wrote:

>  I don't know that a critical section is required here, but if it is we really
>  don't want to get interrupted between reading the counter and calculating the
>  ticks.

Will/does MIPS implement soft critical sections as an alternative to hard 
interrupt disabling, in which case will this change actually have the desired 
effect?  (Note that on i386/amd64, critical_enter can still be interrupted by 
fast interrupt handlers)

Robert