svn commit: r209530 - in user/jmallett/octeon/sys: conf mips/cavium
mips/include mips/mips
Juli Mallett
jmallett at FreeBSD.org
Sat Jun 26 03:15:20 UTC 2010
Author: jmallett
Date: Sat Jun 26 03:15:19 2010
New Revision: 209530
URL: http://svn.freebsd.org/changeset/base/209530
Log:
Instead of using a hackish TARGET_OCTEON option, use a CPU_CNMIPS option to
detect code that needs specific changes for the Cavium Octeon, and presumably
any other cnMIPS platform we would support. This allows removing some includes
of opt_cputype.h, but I have not made an exhaustive check of the remaining
ones.
Modified:
user/jmallett/octeon/sys/conf/options.mips
user/jmallett/octeon/sys/mips/cavium/std.octeon1
user/jmallett/octeon/sys/mips/include/_bus.h
user/jmallett/octeon/sys/mips/include/cache_mipsNN.h
user/jmallett/octeon/sys/mips/include/cpufunc.h
user/jmallett/octeon/sys/mips/include/cpuregs.h
user/jmallett/octeon/sys/mips/mips/bus_space_generic.c
user/jmallett/octeon/sys/mips/mips/cache.c
user/jmallett/octeon/sys/mips/mips/cache_mipsNN.c
user/jmallett/octeon/sys/mips/mips/cpu.c
user/jmallett/octeon/sys/mips/mips/exception.S
user/jmallett/octeon/sys/mips/mips/locore.S
user/jmallett/octeon/sys/mips/mips/machdep.c
user/jmallett/octeon/sys/mips/mips/mainbus.c
user/jmallett/octeon/sys/mips/mips/mpboot.S
user/jmallett/octeon/sys/mips/mips/pm_machdep.c
user/jmallett/octeon/sys/mips/mips/support.S
user/jmallett/octeon/sys/mips/mips/vm_machdep.c
Modified: user/jmallett/octeon/sys/conf/options.mips
==============================================================================
--- user/jmallett/octeon/sys/conf/options.mips Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/conf/options.mips Sat Jun 26 03:15:19 2010 (r209530)
@@ -50,7 +50,6 @@ CFE_ENV opt_global.h
CFE_ENV_SIZE opt_global.h
NOFPU opt_global.h
-TARGET_OCTEON opt_global.h
TARGET_EMULATOR opt_ddb.h
TARGET_XLR_XLS opt_global.h
Modified: user/jmallett/octeon/sys/mips/cavium/std.octeon1
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/std.octeon1 Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/cavium/std.octeon1 Sat Jun 26 03:15:19 2010 (r209530)
@@ -17,6 +17,3 @@ device pci
#device clock
#device obio
#device uart
-
-# Kludge
-options TARGET_OCTEON
Modified: user/jmallett/octeon/sys/mips/include/_bus.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/_bus.h Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/include/_bus.h Sat Jun 26 03:15:19 2010 (r209530)
@@ -34,8 +34,7 @@
/*
* Bus address and size types
*/
-#include "opt_cputype.h"
-#if defined(TARGET_OCTEON) && (defined(__mips_n32) || defined(__mips_o32))
+#if defined(CPU_CNMIPS) && (defined(__mips_n32) || defined(__mips_o32))
typedef uint64_t bus_addr_t;
#else
typedef uintptr_t bus_addr_t;
Modified: user/jmallett/octeon/sys/mips/include/cache_mipsNN.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cache_mipsNN.h Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/include/cache_mipsNN.h Sat Jun 26 03:15:19 2010 (r209530)
@@ -57,7 +57,7 @@ void mipsNN_pdcache_inv_range_16(vm_offs
void mipsNN_pdcache_inv_range_32(vm_offset_t, vm_size_t);
void mipsNN_pdcache_wb_range_16(vm_offset_t, vm_size_t);
void mipsNN_pdcache_wb_range_32(vm_offset_t, vm_size_t);
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
void mipsNN_icache_sync_all_128(void);
void mipsNN_icache_sync_range_128(vm_offset_t, vm_size_t);
void mipsNN_icache_sync_range_index_128(vm_offset_t, vm_size_t);
Modified: user/jmallett/octeon/sys/mips/include/cpufunc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpufunc.h Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/include/cpufunc.h Sat Jun 26 03:15:19 2010 (r209530)
@@ -186,7 +186,7 @@ mips_wr_ ## n(uint32_t a0) \
mips_barrier(); \
} struct __hack
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
static __inline void mips_sync_icache (void)
{
__asm __volatile (
Modified: user/jmallett/octeon/sys/mips/include/cpuregs.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpuregs.h Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/include/cpuregs.h Sat Jun 26 03:15:19 2010 (r209530)
@@ -110,7 +110,7 @@
#define MIPS_XKSEG_END 0xc00000ff80000000
/* CPU dependent mtc0 hazard hook */
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
#define COP0_SYNC nop; nop; nop; nop; nop;
#elif defined(CPU_SB1)
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
Modified: user/jmallett/octeon/sys/mips/mips/bus_space_generic.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/bus_space_generic.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/bus_space_generic.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -198,7 +198,7 @@ static struct bus_space generic_space =
/* Ultra-gross kludge */
#include "opt_cputype.h"
-#if defined(TARGET_OCTEON) && (defined(__mips_n32) || defined(__mips_o32))
+#if defined(CPU_CNMIPS) && (defined(__mips_n32) || defined(__mips_o32))
#include <contrib/octeon-sdk/cvmx.h>
#define rd8(a) cvmx_read64_uint8(a)
#define rd16(a) cvmx_read64_uint16(a)
Modified: user/jmallett/octeon/sys/mips/mips/cache.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/cache.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/cache.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -99,7 +99,7 @@ mips_config_cache(struct mips_cpuinfo *
mips_cache_ops.mco_icache_sync_range_index =
mipsNN_icache_sync_range_index_32;
break;
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
case 128:
mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
mips_cache_ops.mco_icache_sync_range =
@@ -154,7 +154,7 @@ mips_config_cache(struct mips_cpuinfo *
mips_cache_ops.mco_intern_pdcache_wb_range =
mipsNN_pdcache_wb_range_32;
break;
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
case 128:
mips_cache_ops.mco_pdcache_wbinv_all =
mips_cache_ops.mco_intern_pdcache_wbinv_all =
Modified: user/jmallett/octeon/sys/mips/mips/cache_mipsNN.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/cache_mipsNN.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/cache_mipsNN.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -61,7 +61,7 @@ __FBSDID("$FreeBSD$");
#define SYNC __asm volatile("sync")
#endif
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
#define SYNCI mips_sync_icache();
#else
#define SYNCI
@@ -568,7 +568,7 @@ mipsNN_pdcache_wb_range_32(vm_offset_t v
}
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
void
mipsNN_icache_sync_all_128(void)
Modified: user/jmallett/octeon/sys/mips/mips/cpu.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/cpu.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/cpu.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -117,7 +117,7 @@ mips_get_identity(struct mips_cpuinfo *c
cpuinfo->l1.dc_nsets =
1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6);
}
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
/*
* Octeon does 128 byte line-size. But Config-Sel1 doesn't show
* 128 line-size, 1 Set, 64 ways.
Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/exception.S Sat Jun 26 03:15:19 2010 (r209530)
@@ -235,7 +235,7 @@ SlowFault:
#define SAVE_REG(reg, offs, base) \
REG_S reg, CALLFRAME_SIZ + (SZREG * offs) (base)
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
@@ -475,7 +475,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
# Turn off fpu and enter kernel mode
and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB)
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
#endif
mtc0 t0, COP_0_STATUS_REG
@@ -691,7 +691,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r
# Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
#endif
mtc0 t0, COP_0_STATUS_REG
Modified: user/jmallett/octeon/sys/mips/mips/locore.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/locore.S Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/locore.S Sat Jun 26 03:15:19 2010 (r209530)
@@ -88,7 +88,7 @@ VECTOR(_locore, unknown)
/* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */
mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts
-#if defined(TARGET_OCTEON)
+#if defined(CPU_CNMIPS)
/*
* t1: Bits to set explicitly:
* Enable FPU
@@ -162,7 +162,7 @@ VECTOR(_locore, unknown)
sw a2, _C_LABEL(fenvp)
#endif
-#if defined(TARGET_OCTEON) && defined(SMP)
+#if defined(CPU_CNMIPS) && defined(SMP)
.set push
.set mips32r2
rdhwr t2, $0
Modified: user/jmallett/octeon/sys/mips/mips/machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/machdep.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/machdep.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -347,7 +347,7 @@ mips_vector_init(void)
bcopy(MipsTLBMiss, (void *)TLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
-#if defined(TARGET_OCTEON) || defined(TARGET_XLR_XLS)
+#if defined(CPU_CNMIPS) || defined(TARGET_XLR_XLS)
/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
bcopy(MipsTLBMiss, (void *)XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
Modified: user/jmallett/octeon/sys/mips/mips/mainbus.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mainbus.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/mainbus.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -251,7 +251,7 @@ mainbus_activate_resource(device_t bus,
/*
* If this is a memory resource, map it into the kernel.
*/
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
uint64_t temp;
#endif
if (rman_get_bustag(r) == MIPS_BUS_SPACE_MEM) {
@@ -267,7 +267,7 @@ mainbus_activate_resource(device_t bus,
+ poffs;
}
rman_set_virtual(r, vaddr);
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
temp = 0x0000000000000000;
temp |= (uint32_t)vaddr;
rman_set_bushandle(r, (bus_space_handle_t) temp);
Modified: user/jmallett/octeon/sys/mips/mips/mpboot.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mpboot.S Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/mpboot.S Sat Jun 26 03:15:19 2010 (r209530)
@@ -36,7 +36,7 @@
.set noat
.set noreorder
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
Modified: user/jmallett/octeon/sys/mips/mips/pm_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pm_machdep.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/pm_machdep.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -488,7 +488,7 @@ exec_setregs(struct thread *td, struct i
#if defined(__mips_n32) || defined(__mips_n64)
td->td_frame->sr |= SR_PX;
#endif
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX |
MIPS_SR_KX | MIPS_SR_SX;
#endif
Modified: user/jmallett/octeon/sys/mips/mips/support.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/support.S Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/support.S Sat Jun 26 03:15:19 2010 (r209530)
@@ -1431,7 +1431,7 @@ LEAF(casuptr)
END(casuptr)
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
/*
* void octeon_enable_shadow(void)
* turns on access to CC and CCRes
Modified: user/jmallett/octeon/sys/mips/mips/vm_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/vm_machdep.c Sat Jun 26 03:11:29 2010 (r209529)
+++ user/jmallett/octeon/sys/mips/mips/vm_machdep.c Sat Jun 26 03:15:19 2010 (r209530)
@@ -161,7 +161,7 @@ cpu_fork(register struct thread *td1,reg
td2->td_md.md_tls = td1->td_md.md_tls;
td2->td_md.md_saved_intr = MIPS_SR_INT_IE;
td2->td_md.md_spinlock_count = 1;
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
#endif
@@ -364,7 +364,7 @@ cpu_set_upcall(struct thread *td, struct
/* Dont set IE bit in SR. sched lock release will take care of it */
pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status();
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT |
MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
#endif
@@ -426,7 +426,7 @@ cpu_set_upcall_kse(struct thread *td, vo
*/
tf->sr = SR_KSU_USER | SR_EXL | (SR_INT_MASK & mips_rd_status()) |
MIPS_SR_INT_IE;
-#ifdef TARGET_OCTEON
+#ifdef CPU_CNMIPS
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS32_SR_PX | MIPS_SR_UX |
MIPS_SR_KX;
#endif
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