svn commit: r207367 - in user/jmallett/octeon/sys/mips: cavium conf
Juli Mallett
jmallett at FreeBSD.org
Thu Apr 29 10:26:54 UTC 2010
Author: jmallett
Date: Thu Apr 29 10:26:53 2010
New Revision: 207367
URL: http://svn.freebsd.org/changeset/base/207367
Log:
Start work on PCI. Enough to enumerate the devices in my systems.
Added:
user/jmallett/octeon/sys/mips/cavium/octopci.c
user/jmallett/octeon/sys/mips/cavium/octopcireg.h
Modified:
user/jmallett/octeon/sys/mips/cavium/files.octeon1
user/jmallett/octeon/sys/mips/cavium/std.octeon1
user/jmallett/octeon/sys/mips/conf/OCTEON1.hints
Modified: user/jmallett/octeon/sys/mips/cavium/files.octeon1
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/files.octeon1 Thu Apr 29 10:04:00 2010 (r207366)
+++ user/jmallett/octeon/sys/mips/cavium/files.octeon1 Thu Apr 29 10:26:53 2010 (r207367)
@@ -26,6 +26,8 @@ mips/cavium/octe/ethernet-xaui.c option
mips/cavium/octe/octe.c optional octe
mips/cavium/octe/octebus.c optional octe
+mips/cavium/octopci.c optional pci
+
contrib/octeon-sdk/cvmx-cmd-queue.c optional octe
contrib/octeon-sdk/cvmx-fpa.c optional octe
contrib/octeon-sdk/cvmx-helper.c optional octe
Added: user/jmallett/octeon/sys/mips/cavium/octopci.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ user/jmallett/octeon/sys/mips/cavium/octopci.c Thu Apr 29 10:26:53 2010 (r207367)
@@ -0,0 +1,230 @@
+/*-
+ * Copyright (c) 2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/interrupt.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+#include <machine/pmap.h>
+
+#include <contrib/octeon-sdk/cvmx.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <dev/pci/pcib_private.h>
+
+#include <mips/cavium/octopcireg.h>
+
+#include "pcib_if.h"
+
+struct octopci_softc {
+ device_t sc_dev;
+ unsigned sc_domain;
+ unsigned sc_bus;
+};
+
+static void octopci_identify(driver_t *, device_t);
+static int octopci_probe(device_t);
+static int octopci_attach(device_t);
+static int octopci_read_ivar(device_t, device_t, int, uintptr_t *);
+static int octopci_maxslots(device_t);
+static uint32_t octopci_read_config(device_t, u_int, u_int, u_int, u_int, int);
+static void octopci_write_config(device_t, u_int, u_int, u_int, u_int, uint32_t, int);
+
+static uint64_t octopci_cs_addr(unsigned, unsigned, unsigned, unsigned);
+
+static void
+octopci_identify(driver_t *drv, device_t parent)
+{
+ BUS_ADD_CHILD(parent, 0, "pcib", 0);
+}
+
+static int
+octopci_probe(device_t dev)
+{
+ if (device_get_unit(dev) != 0)
+ return (ENXIO);
+ /* XXX Check sysinfo flag. */
+ device_set_desc(dev, "Cavium Octeon PCI bridge");
+ return (0);
+}
+
+static int
+octopci_attach(device_t dev)
+{
+ struct octopci_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->sc_dev = dev;
+ sc->sc_domain = 0;
+ sc->sc_bus = 0;
+
+ device_add_child(dev, "pci", 0);
+
+ return (bus_generic_attach(dev));
+}
+
+static int
+octopci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
+{
+ struct octopci_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ switch (which) {
+ case PCIB_IVAR_DOMAIN:
+ *result = sc->sc_domain;
+ return (0);
+ case PCIB_IVAR_BUS:
+ *result = sc->sc_bus;
+ return (0);
+
+ }
+ return (ENOENT);
+}
+
+static int
+octopci_maxslots(device_t dev)
+{
+ return (PCI_SLOTMAX);
+}
+
+static uint32_t
+octopci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ int bytes)
+{
+ struct octopci_softc *sc;
+ uint64_t addr;
+ uint32_t data;
+
+ sc = device_get_softc(dev);
+
+ addr = octopci_cs_addr(bus, slot, func, reg);
+
+ switch (bytes) {
+ case 4:
+ data = le32toh(cvmx_read64_uint32(addr));
+ return (data);
+ case 2:
+ data = le16toh(cvmx_read64_uint16(addr));
+ return (data);
+ case 1:
+ data = cvmx_read64_uint8(addr);
+ return (data);
+ default:
+ return ((uint32_t)-1);
+ }
+}
+
+static void
+octopci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
+ uint32_t data, int bytes)
+{
+ struct octopci_softc *sc;
+ uint64_t addr;
+
+ sc = device_get_softc(dev);
+
+ addr = octopci_cs_addr(bus, slot, func, reg);
+
+ switch (bytes) {
+ case 4:
+ cvmx_write64_uint32(addr, htole32(data));
+ return;
+ case 2:
+ cvmx_write64_uint16(addr, htole16(data));
+ return;
+ case 1:
+ cvmx_write64_uint8(addr, data);
+ return;
+ default:
+ return;
+ }
+}
+
+static uint64_t
+octopci_cs_addr(unsigned bus, unsigned slot, unsigned func, unsigned reg)
+{
+ octeon_pci_config_space_address_t pci_addr;
+
+ pci_addr.u64 = 0;
+ pci_addr.s.upper = 2;
+ pci_addr.s.io = 1;
+ pci_addr.s.did = 3;
+ pci_addr.s.subdid = CVMX_OCT_SUBDID_PCI_CFG;
+ pci_addr.s.endian_swap = 1;
+ pci_addr.s.bus = bus;
+ pci_addr.s.dev = slot;
+ pci_addr.s.func = func;
+ pci_addr.s.reg = reg;
+
+ return (pci_addr.u64);
+}
+
+static device_method_t octopci_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, octopci_identify),
+ DEVMETHOD(device_probe, octopci_probe),
+ DEVMETHOD(device_attach, octopci_attach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, octopci_read_ivar),
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+
+ /* pcib interface */
+ DEVMETHOD(pcib_maxslots, octopci_maxslots),
+ DEVMETHOD(pcib_read_config, octopci_read_config),
+ DEVMETHOD(pcib_write_config, octopci_write_config),
+
+ {0, 0}
+};
+
+static driver_t octopci_driver = {
+ "pcib",
+ octopci_methods,
+ sizeof(struct octopci_softc),
+};
+static devclass_t octopci_devclass;
+DRIVER_MODULE(octopci, ciu, octopci_driver, octopci_devclass, 0, 0);
Added: user/jmallett/octeon/sys/mips/cavium/octopcireg.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ user/jmallett/octeon/sys/mips/cavium/octopcireg.h Thu Apr 29 10:26:53 2010 (r207367)
@@ -0,0 +1,98 @@
+/***********************license start************************************
+ * Copyright (c) 2005-2007 Cavium Networks (support at cavium.com). All rights
+ * reserved.
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * * Neither the name of Cavium Networks nor the names of
+ * its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ *
+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
+ * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
+ * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
+ * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
+ * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
+ * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
+ * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
+ * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
+ * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
+ * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
+ *
+ *
+ * For any questions regarding licensing please contact marketing at caviumnetworks.com
+ *
+ ***********************license end**************************************/
+
+#ifndef _CAVIUM_OCTOPCIREG_H_
+#define _CAVIUM_OCTOPCIREG_H_
+
+/**
+ * This is the bit decoding used for the Octeon PCI controller addresses for config space
+ */
+typedef union
+{
+ uint64_t u64;
+ uint64_t * u64_ptr;
+ uint32_t * u32_ptr;
+ uint16_t * u16_ptr;
+ uint8_t * u8_ptr;
+ struct
+ {
+ uint64_t upper : 2;
+ uint64_t reserved : 13;
+ uint64_t io : 1;
+ uint64_t did : 5;
+ uint64_t subdid : 3;
+ uint64_t reserved2 : 4;
+ uint64_t endian_swap : 2;
+ uint64_t reserved3 : 10;
+ uint64_t bus : 8;
+ uint64_t dev : 5;
+ uint64_t func : 3;
+ uint64_t reg : 8;
+ } s;
+} octeon_pci_config_space_address_t;
+
+typedef union
+{
+ uint64_t u64;
+ uint32_t * u32_ptr;
+ uint16_t * u16_ptr;
+ uint8_t * u8_ptr;
+ struct
+ {
+ uint64_t upper : 2;
+ uint64_t reserved : 13;
+ uint64_t io : 1;
+ uint64_t did : 5;
+ uint64_t subdid : 3;
+ uint64_t reserved2 : 4;
+ uint64_t endian_swap : 2;
+ uint64_t res1 : 1;
+ uint64_t port : 1;
+ uint64_t addr : 32;
+ } s;
+} octeon_pci_io_space_address_t;
+
+
+#define CVMX_OCT_SUBDID_PCI_CFG 1
+#define CVMX_OCT_SUBDID_PCI_IO 2
+#define CVMX_OCT_SUBDID_PCI_MEM1 3
+#define CVMX_OCT_SUBDID_PCI_MEM2 4
+#define CVMX_OCT_SUBDID_PCI_MEM3 5
+#define CVMX_OCT_SUBDID_PCI_MEM4 6
+
+#endif /* !_CAVIUM_OCTOPCIREG_H_ */
Modified: user/jmallett/octeon/sys/mips/cavium/std.octeon1
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/std.octeon1 Thu Apr 29 10:04:00 2010 (r207366)
+++ user/jmallett/octeon/sys/mips/cavium/std.octeon1 Thu Apr 29 10:26:53 2010 (r207367)
@@ -10,7 +10,7 @@ files "../cavium/files.octeon1"
#
#
cpu CPU_MIPS4KC
-#device pci
+device pci
#device ata
#device atadisk
Modified: user/jmallett/octeon/sys/mips/conf/OCTEON1.hints
==============================================================================
--- user/jmallett/octeon/sys/mips/conf/OCTEON1.hints Thu Apr 29 10:04:00 2010 (r207366)
+++ user/jmallett/octeon/sys/mips/conf/OCTEON1.hints Thu Apr 29 10:26:53 2010 (r207367)
@@ -10,5 +10,3 @@ hint.obio.0.flags="0x1"
hint.uart.0.at="obio"
hint.uart.0.maddr="0x1"
hint.uart.0.flags="0x1"
-hint.pcib.0.at="nexus"
-hint.pci.0.at="pcib"
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