svn commit: r206978 - user/jmallett/octeon/sys/mips/cavium
Juli Mallett
jmallett at FreeBSD.org
Wed Apr 21 04:44:09 UTC 2010
Author: jmallett
Date: Wed Apr 21 04:44:08 2010
New Revision: 206978
URL: http://svn.freebsd.org/changeset/base/206978
Log:
Centralize and correct MBOX IRQ unmasking. We want this to go to hard
interrupt #1 not hard interrupt #0.
Modified:
user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c
user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
Modified: user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Wed Apr 21 04:35:23 2010 (r206977)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Wed Apr 21 04:44:08 2010 (r206978)
@@ -209,6 +209,13 @@ octeon_ciu_reset(void)
cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
+
+#ifdef SMP
+ /* Enable the MBOX interrupts. */
+ cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
+ (1ull << (CVMX_IRQ_MBOX0 - 8)) |
+ (1ull << (CVMX_IRQ_MBOX1 - 8)));
+#endif
}
static void
@@ -307,10 +314,9 @@ platform_start(__register_t a0, __regist
#ifdef SMP
/*
- * Clear any pending IPIs and enable the IPI interrupt.
+ * Clear any pending IPIs.
*/
oct_write64(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
- cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
#endif
}
Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Wed Apr 21 04:35:23 2010 (r206977)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Wed Apr 21 04:44:08 2010 (r206978)
@@ -75,12 +75,14 @@ platform_init_ap(int cpuid)
mips_wr_ebase(0x80000000 | cpuid);
/*
- * Set up interrupts, clear IPIs and unmask the IPI interrupt.
+ * Clear any pending IPIs.
*/
- octeon_ciu_reset();
-
oct_write64(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
- cvmx_interrupt_unmask_irq(CVMX_IRQ_MBOX0);
+
+ /*
+ * Set up interrupts.
+ */
+ octeon_ciu_reset();
mips_wbflush();
}
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