svn commit: r206674 - in user/jmallett/octeon/sys/mips: cavium include mips

[Juli Mallett]

Author: jmallett
Date: Thu Apr 15 18:30:21 2010
New Revision: 206674
URL: http://svn.freebsd.org/changeset/base/206674

Log:
  o) Set the exception base on Octeon to the right thing on each AP.
  o) Do a sync before accessing (and after setting) variables set for the AP
     by the bootstrap processor.  Otherwise we sometimes see a NULL dpcpu in
     smp_init_secondary().
     XXX All of the shared variables here really ought to be manipulated via
         atomic operations.
  o) Clear BEV on APs, too.

Modified:
  user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
  user/jmallett/octeon/sys/mips/include/cpufunc.h
  user/jmallett/octeon/sys/mips/mips/mp_machdep.c
  user/jmallett/octeon/sys/mips/mips/mpboot.S

Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c	Thu Apr 15 17:46:51 2010	(r206673)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c	Thu Apr 15 18:30:21 2010	(r206674)
@@ -61,6 +61,12 @@ platform_ipi_intrnum(void)
 void
 platform_init_ap(int cpuid)
 {
+	/*
+	 * Set the exception base.
+	 *
+	 * XXX Low bits seem to be used for cpuid?
+	 */
+	mips_wr_prid1(0x80000000);
 }
 
 int

Modified: user/jmallett/octeon/sys/mips/include/cpufunc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpufunc.h	Thu Apr 15 17:46:51 2010	(r206673)
+++ user/jmallett/octeon/sys/mips/include/cpufunc.h	Thu Apr 15 18:30:21 2010	(r206674)
@@ -218,6 +218,8 @@ MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB
 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
 #endif
 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
+/* XXX 64-bit?  */
+MIPS_RDRW32_COP0_SEL(prid, MIPS_COP_0_PRID, 1);
 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
 MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
 MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
@@ -232,7 +234,6 @@ MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0
 MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 2);
 MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 3);
 
-
 #undef	MIPS_RDRW32_COP0
 
 static __inline register_t

Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Thu Apr 15 17:46:51 2010	(r206673)
+++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Thu Apr 15 18:30:21 2010	(r206674)
@@ -157,6 +157,8 @@ start_ap(int cpuid)
 	cpus = mp_naps;
 	dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
 
+	mips_sync();
+
 	if (platform_start_ap(cpuid) != 0)
 		return (-1);			/* could not start AP */
 
@@ -246,6 +248,8 @@ smp_init_secondary(u_int32_t cpuid)
 	mips_dcache_wbinv_all();
 	mips_icache_sync_all();
 
+	mips_sync();
+
 	mips_wr_entryhi(0);
 
 	pcpu_init(PCPU_ADDR(cpuid), cpuid, sizeof(struct pcpu));

Modified: user/jmallett/octeon/sys/mips/mips/mpboot.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mpboot.S	Thu Apr 15 17:46:51 2010	(r206673)
+++ user/jmallett/octeon/sys/mips/mips/mpboot.S	Thu Apr 15 18:30:21 2010	(r206674)
@@ -41,7 +41,7 @@
 	mfc0    a0, COP_0_STATUS_REG    ;\
 	li      a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
 	or      a0, a0, a2	        ; \
-	li      a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER)   ; \
+	li      a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV)   ; \
 	and     a0, a0, a2              ; \
         mtc0    a0, COP_0_STATUS_REG    
 #else