svn commit: r206644 - in user/jmallett/octeon/sys/mips: cavium mips
Juli Mallett
jmallett at FreeBSD.org
Thu Apr 15 02:59:22 UTC 2010
Author: jmallett
Date: Thu Apr 15 02:59:21 2010
New Revision: 206644
URL: http://svn.freebsd.org/changeset/base/206644
Log:
o) Add stub SMP-related functions for Octeon to fix SMP build of it.
o) Note a place where we need an exception.S-style CLEAR_STATUS in mpboot.
Added:
user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
Modified:
user/jmallett/octeon/sys/mips/cavium/asm_octeon.S
user/jmallett/octeon/sys/mips/cavium/files.octeon1
user/jmallett/octeon/sys/mips/mips/mpboot.S
Modified: user/jmallett/octeon/sys/mips/cavium/asm_octeon.S
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/asm_octeon.S Thu Apr 15 02:44:16 2010 (r206643)
+++ user/jmallett/octeon/sys/mips/cavium/asm_octeon.S Thu Apr 15 02:59:21 2010 (r206644)
@@ -1,182 +1,39 @@
-/***********************license start***************
- * Copyright (c) 2003-2008 Cavium Networks (support at cavium.com). All rights
- * reserved.
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
*
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following
- * disclaimer in the documentation and/or other materials provided
- * with the distribution.
- *
- * * Neither the name of Cavium Networks nor the names of
- * its contributors may be used to endorse or promote products
- * derived from this software without specific prior written
- * permission.
- *
- * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
- * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
- * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
- * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
- * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
- * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
- * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
- * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
- * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
- * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
- *
- *
- * For any questions regarding licensing please contact marketing at caviumnetworks.com
- *
- ***********************license end**************************************/
-
-/* $FreeBSD$ */
-
-#include <machine/asm.h>
-#include <machine/cache_r4k.h>
-#include <machine/cpuregs.h>
-#include <machine/param.h>
-#include <machine/pte.h>
-
-#include "assym.s"
-
-
-
-#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
- mfc0 reg, MIPS_COP_0_STATUS; \
- nop; \
- move reg3, reg; \
- li reg2, ~MIPS_SR_INT_IE; \
- and reg, reg2, reg; \
- mtc0 reg, MIPS_COP_0_STATUS; \
- COP0_SYNC
-
-
-
-#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
- mfc0 reg, MIPS_COP_0_STATUS; \
- nop; \
- or reg, reg, reg3; \
- mtc0 reg, MIPS_COP_0_STATUS; \
- COP0_SYNC
-
-
-#define PUSHR(reg) \
- addiu sp,sp,-16 ; \
- sd reg, 8(sp) ; \
- nop ;
-
-#define POPR(reg) \
- ld reg, 8(sp) ; \
- addiu sp,sp,16 ; \
- nop ;
-
-
-
-
-/*
- * octeon_ciu_get_interrupt_reg_addr
- *
- * Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr
- * a0 = ciu Int-X: 0/1
- * a1 = ciu EN-0: 0/1
+ * $FreeBSD$
*/
-LEAF(octeon_ciu_get_interrupt_reg_addr)
- .set noreorder
- .set mips3
-
- beqz a0, ciu_get_interrupt_reg_addr_Int_0
- nop
-
-ciu_get_interrupt_reg_addr_Int_1:
- beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0
- nop
-
-ciu_get_interrupt_reg_addr_Int_1_En1:
- li a0, OCTEON_CIU_ADDR_HI
- dsll32 a0, a0, 0
- nop
- ori a0, OCTEON_CIU_EN1_INT1_LO
- j ciu_get_interrupt_reg_addr_ret
- nop
-
-ciu_get_interrupt_reg_addr_Int_1_En_0:
- li a0, OCTEON_CIU_ADDR_HI
- dsll32 a0, a0, 0
- nop
- ori a0, OCTEON_CIU_EN0_INT1_LO
- j ciu_get_interrupt_reg_addr_ret
- nop
-
-ciu_get_interrupt_reg_addr_Int_0:
- beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0
- nop
-
-ciu_get_interrupt_reg_addr_Int_0_En_1:
- li a0, OCTEON_CIU_ADDR_HI
- dsll32 a0, a0, 0
- nop
- ori a0, OCTEON_CIU_EN1_INT0_LO
- j ciu_get_interrupt_reg_addr_ret
- nop
-
-ciu_get_interrupt_reg_addr_Int_0_En_0:
- li a0, OCTEON_CIU_ADDR_HI
- dsll32 a0, a0, 0
- nop
- ori a0, OCTEON_CIU_EN0_INT0_LO
-
-
-ciu_get_interrupt_reg_addr_ret:
- j ra
- nop
-
- .set mips0
- .set reorder
-END(octeon_ciu_get_interrupt_reg_addr)
-
+#include <machine/asm.h>
-
+#ifdef SMP
/*
- * octeon_ciu_mask_all_interrupts
- *
- * a0 = ciu Interrupt-X: 0/1
- * a1 = ciu Enable-X: 0/1
+ * This function must be implemented in assembly because it is called early
+ * in AP boot without a valid stack.
*/
-LEAF(octeon_ciu_mask_all_interrupts)
- .set noreorder
- .set mips3
-
- PUSHR(ra)
- PUSHR(s0)
-
- move t0, a0
- move t1, a1
- li a0, MIPS_SR_INT_IE
- CPU_DISABLE_INTERRUPTS(a2, a1, s0)
- move a0, t0
- move t1, a1
- jal octeon_ciu_get_interrupt_reg_addr
- nop
- ld a2, 0(a0) # Dummy read
- nop
- move a2, zero # Clear all
- sd a2, 0(a0) # Write new Enable bits
- nop
- CPU_ENABLE_INTERRUPTS(a2, s0)
-
- POPR(s0)
- POPR(ra)
- j ra # Return
- nop # (bd slot)
-
- .set mips0
- .set reorder
-END(octeon_ciu_mask_all_interrupts)
-
+LEAF(platform_processor_id)
+ li v0, 0
+ jr ra
+END(platform_processor_id)
+#endif
Modified: user/jmallett/octeon/sys/mips/cavium/files.octeon1
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/files.octeon1 Thu Apr 15 02:44:16 2010 (r206643)
+++ user/jmallett/octeon/sys/mips/cavium/files.octeon1 Thu Apr 15 02:59:21 2010 (r206644)
@@ -1,6 +1,7 @@
# $FreeBSD$
# Octeon Support Files
#
+mips/cavium/asm_octeon.S optional smp
mips/cavium/dev/rgmii/octeon_fpa.c optional rgmii
mips/cavium/dev/rgmii/octeon_ipd.c optional rgmii
mips/cavium/dev/rgmii/octeon_pko.c optional rgmii
@@ -8,6 +9,7 @@ mips/cavium/dev/rgmii/octeon_rgmx.c opt
mips/cavium/obio.c optional uart
mips/cavium/octeon_ebt3000_cf.c optional cf
mips/cavium/octeon_machdep.c standard
+mips/cavium/octeon_mp.c optional smp
mips/cavium/uart_bus_octeonusart.c optional uart
mips/cavium/uart_cpu_octeonusart.c optional uart
mips/cavium/uart_dev_oct16550.c optional uart
Added: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Thu Apr 15 02:59:21 2010 (r206644)
@@ -0,0 +1,75 @@
+/*-
+ * Copyright (c) 2004-2010 Juli Mallett <jmallett at FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+
+#include <machine/hwfunc.h>
+#include <machine/smp.h>
+
+void
+platform_ipi_send(int cpuid)
+{
+ panic("%s: not yet implemented.", __func__);
+}
+
+void
+platform_ipi_clear(void)
+{
+ panic("%s: not yet implemented.", __func__);
+}
+
+int
+platform_ipi_intrnum(void)
+{
+ panic("%s: not yet implemented.", __func__);
+}
+
+void
+platform_init_ap(int cpuid)
+{
+ panic("%s: not yet implemented.", __func__);
+
+ KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
+}
+
+int
+platform_num_processors(void)
+{
+ panic("%s: not yet implemented.", __func__);
+}
+
+int
+platform_start_ap(int cpuid)
+{
+ panic("%s: not yet implemented.", __func__);
+}
Modified: user/jmallett/octeon/sys/mips/mips/mpboot.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mpboot.S Thu Apr 15 02:44:16 2010 (r206643)
+++ user/jmallett/octeon/sys/mips/mips/mpboot.S Thu Apr 15 02:59:21 2010 (r206644)
@@ -37,6 +37,7 @@
.set noreorder
GLOBAL(mpentry)
+ /* XXX On n64 this will be a problem. */
mtc0 zero, COP_0_STATUS_REG /* disable interrupts */
mtc0 zero, COP_0_CAUSE_REG /* clear soft interrupts */
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