svn commit: r206253 - in user/jmallett/octeon/sys/mips: include mips

[Juli Mallett]

Author: jmallett
Date: Tue Apr  6 08:29:58 2010
New Revision: 206253
URL: http://svn.freebsd.org/changeset/base/206253

Log:
  o) Make calling convention for trap() and cpu_intr() the same, reduce diffs
     between KernGenException and KernIntr.

Modified:
  user/jmallett/octeon/sys/mips/include/intr_machdep.h
  user/jmallett/octeon/sys/mips/mips/exception.S
  user/jmallett/octeon/sys/mips/mips/intr_machdep.c

Modified: user/jmallett/octeon/sys/mips/include/intr_machdep.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/intr_machdep.h	Tue Apr  6 07:49:06 2010	(r206252)
+++ user/jmallett/octeon/sys/mips/include/intr_machdep.h	Tue Apr  6 08:29:58 2010	(r206253)
@@ -43,7 +43,7 @@ void cpu_establish_hardintr(const char *
     void *, int, int, void **);
 void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*), 
     void *, int, int, void **);
-void cpu_intr(struct trapframe *);
+register_t cpu_intr(struct trapframe *);
 
 /*
  * Allow a platform to override the default hard interrupt mask and unmask

Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S	Tue Apr  6 07:49:06 2010	(r206252)
+++ user/jmallett/octeon/sys/mips/mips/exception.S	Tue Apr  6 08:29:58 2010	(r206253)
@@ -591,24 +591,22 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_S
 	PTR_SUBU	sp, sp, KERN_EXC_FRAME_SIZE
 	.mask	0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE)
 /*
- * Save the relevant kernel registers onto the stack.
+ *  Save CPU state, building 'frame'.
  */
 	SAVE_CPU
-        
 /*
- * Call the interrupt handler.
+ *  Call the interrupt handler. a0 points at the saved frame.
  */
 	PTR_LA	gp, _C_LABEL(_gp)
-	PTR_ADDU a0, sp, CALLFRAME_SIZ
 	PTR_LA	k0, _C_LABEL(cpu_intr)
 	jalr	k0
-	REG_S	a3, CALLFRAME_RA + KERN_REG_SIZE(sp)
-	/* Why no AST processing here? */
+	REG_S	a3, CALLFRAME_RA + KERN_REG_SIZE(sp)		# for debugging
 
 	/*
 	 * Update interrupt mask in saved status register
 	 * Some of interrupts could be disabled by
-	 * intr filters
+	 * intr filters if interrupts are enabled later
+	 * in trap handler
 	 */
 	mfc0	a0, COP_0_STATUS_REG
 	and	a0, a0, SR_INT_MASK
@@ -616,12 +614,7 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_S
 	and	a1, a1, ~SR_INT_MASK
 	or	a1, a1, a0
 	SAVE_REG(a1, SR, sp)
-
-/*
- * Restore registers and return from the interrupt.
- */
-	REG_L	v0, CALLFRAME_RA + KERN_REG_SIZE(sp)
-	RESTORE_CPU
+	RESTORE_CPU			# v0 contains the return address.
 	sync
 	eret
 	.set	at

Modified: user/jmallett/octeon/sys/mips/mips/intr_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/intr_machdep.c	Tue Apr  6 07:49:06 2010	(r206252)
+++ user/jmallett/octeon/sys/mips/mips/intr_machdep.c	Tue Apr  6 08:29:58 2010	(r206253)
@@ -213,7 +213,7 @@ cpu_establish_softintr(const char *name,
 	mips_intrcnt_setname(mips_intr_counters[irq], event->ie_fullname);
 }
 
-void
+register_t
 cpu_intr(struct trapframe *tf)
 {
 	struct intr_event *event;
@@ -266,4 +266,6 @@ cpu_intr(struct trapframe *tf)
 	KASSERT(i == 0, ("all interrupts handled"));
 
 	critical_exit();
+
+	return (tf->pc);
 }